From d96a980441a70168a8ead0a0f23c4c63725da5fa Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 16 Apr 2008 00:12:39 +0100 Subject: [PATCH] [ARM] 4986/1: S3C24XX: Simtec machines need UCLK as parent to DCLK All current Simtec designs source the DCLK outputs from the UPLL. This means the DCLK's parent must be set to UPLL so that anything enabling and disabling an UPLL sourced clock does not shutdown the DCLK due to missing open counts. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/mach-bast.c | 4 ++-- arch/arm/mach-s3c2410/mach-vr1000.c | 2 +- arch/arm/mach-s3c2440/mach-anubis.c | 4 ++-- arch/arm/mach-s3c2440/mach-osiris.c | 5 +++-- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index b45fb65889..518727d0df 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -592,10 +592,10 @@ static void __init bast_map_io(void) { /* initialise the clocks */ - s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.parent = &clk_upll; s3c24xx_dclk0.rate = 12*1000*1000; - s3c24xx_dclk1.parent = NULL; + s3c24xx_dclk1.parent = &clk_upll; s3c24xx_dclk1.rate = 24*1000*1000; s3c24xx_clkout0.parent = &s3c24xx_dclk0; diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 3aade7b78f..c56423373f 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c @@ -393,7 +393,7 @@ static void __init vr1000_map_io(void) { /* initialise clock sources */ - s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.parent = &clk_upll; s3c24xx_dclk0.rate = 12*1000*1000; s3c24xx_dclk1.parent = NULL; diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index 3d3dfa95db..47258915a2 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c @@ -413,10 +413,10 @@ static void __init anubis_map_io(void) { /* initialise the clocks */ - s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.parent = &clk_upll; s3c24xx_dclk0.rate = 12*1000*1000; - s3c24xx_dclk1.parent = NULL; + s3c24xx_dclk1.parent = &clk_upll; s3c24xx_dclk1.rate = 24*1000*1000; s3c24xx_clkout0.parent = &s3c24xx_dclk0; diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index 78af766498..8a8acdbd07 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -344,10 +345,10 @@ static void __init osiris_map_io(void) /* initialise the clocks */ - s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.parent = &clk_upll; s3c24xx_dclk0.rate = 12*1000*1000; - s3c24xx_dclk1.parent = NULL; + s3c24xx_dclk1.parent = &clk_upll; s3c24xx_dclk1.rate = 24*1000*1000; s3c24xx_clkout0.parent = &s3c24xx_dclk0; -- 2.39.5