From d7a1944e8da5e91859b98259189aaaa4d8b7fa07 Mon Sep 17 00:00:00 2001 From: Gary Hade Date: Mon, 6 Nov 2006 15:39:23 -0800 Subject: [PATCH] [CPUFREQ] speedstep-centrino should ignore upper performance control bits On some systems such as the IBM x3650 there are bits set in the upper half of the control values provided by the _PSS object. These bits are only relevant for cpufreq drivers that use IO ports which are not currently supported by the speedstep-centrino driver. The current MSR oriented code assumes that upper bits are not set and thus fails to work correctly when they are. e.g. the control and status value equality check fails even though the ACPI spec allows the inequality. Signed-off-by: Gary Hade Signed-off-by: Dave Jones --- arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c b/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c index d2d9caf00a..e3fa03ab19 100644 --- a/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c +++ b/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c @@ -463,6 +463,10 @@ static int centrino_cpu_init_acpi(struct cpufreq_policy *policy) } for (i=0; istate_count; i++) { + /* clear high bits (set by some BIOSes) that are non-relevant and + problematic for this driver's MSR only frequency transition code */ + p->states[i].control &= 0xffff; + if (p->states[i].control != p->states[i].status) { dprintk("Different control (%llu) and status values (%llu)\n", p->states[i].control, p->states[i].status); -- 2.39.5