From b85b82d980526d683dc3b39f2ac1f447fa84a105 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 24 Apr 2008 06:13:37 +0800 Subject: [PATCH] [Blackfin] arch: fix bug - Section data_l1_cacheline_aligned should be defined in link script of kernel http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3978 Section data_l1_cacheline_aligned should be defined in link script of kernel, when L1 data sram bank A is not available. In bf536 with all data cache is enabled, there is no L1 data sram. Current link script won't define section data_l1.cacheline_aligned in this case. But, if user select put cacheline_aligned data into l1 sram in kernel menuconfig, these data will be dropped and access to these data will trigger data CPLB exception. Do panic in l1 relocation code as well. Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu --- arch/blackfin/kernel/setup.c | 6 +++--- arch/blackfin/kernel/vmlinux.lds.S | 5 +++++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index fafaccb321..c494495af4 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -107,7 +107,7 @@ void __init bf53x_relocate_l1_mem(void) l1_code_length = _etext_l1 - _stext_l1; if (l1_code_length > L1_CODE_LENGTH) - l1_code_length = L1_CODE_LENGTH; + panic("L1 Instruction SRAM Overflow\n"); /* cannot complain as printk is not available as yet. * But we can continue booting and complain later! */ @@ -117,14 +117,14 @@ void __init bf53x_relocate_l1_mem(void) l1_data_a_length = _ebss_l1 - _sdata_l1; if (l1_data_a_length > L1_DATA_A_LENGTH) - l1_data_a_length = L1_DATA_A_LENGTH; + panic("L1 Data SRAM Bank A Overflow\n"); /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */ dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length); l1_data_b_length = _ebss_b_l1 - _sdata_b_l1; if (l1_data_b_length > L1_DATA_B_LENGTH) - l1_data_b_length = L1_DATA_B_LENGTH; + panic("L1 Data SRAM Bank B Overflow\n"); /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */ dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index 7a1200328a..288dfdbfb6 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S @@ -83,6 +83,11 @@ SECTIONS . = ALIGN(32); *(.data.cacheline_aligned) +#if !L1_DATA_A_LENGTH + . = ALIGN(32); + *(.data_l1.cacheline_aligned) +#endif + DATA_DATA *(.data.*) CONSTRUCTORS -- 2.39.5