From 84e65b0a84a2c856bef36f13d122047678408b0a Mon Sep 17 00:00:00 2001 From: Richard Kennedy Date: Fri, 4 Jul 2008 13:56:16 +0100 Subject: [PATCH] x86: cacheline_align tss_struct The manual padding to align on cacheline size only worked in 32 bit In 64 bit the structure was not aligned and contained wasted space. use the compiler ____cachline_aligned to save space & properly align this structure. x86_64_default size goes from 9136 -> 8960 x86_64_AMD size goes from 9136 -> 8896 built & running on 2.6.26-rc8. Signed-off-by: Richard Kennedy Signed-off-by: Ingo Molnar --- include/asm-x86/processor.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h index 559105220a..4ab2ede6f4 100644 --- a/include/asm-x86/processor.h +++ b/include/asm-x86/processor.h @@ -262,16 +262,12 @@ struct tss_struct { unsigned long io_bitmap_max; struct thread_struct *io_bitmap_owner; - /* - * Pad the TSS to be cacheline-aligned (size is 0x100): - */ - unsigned long __cacheline_filler[35]; /* * .. and then another 0x100 bytes for the emergency kernel stack: */ unsigned long stack[64]; -} __attribute__((packed)); +} ____cacheline_aligned; DECLARE_PER_CPU(struct tss_struct, init_tss); -- 2.39.5