From 6ba07e590d1f841a5d0539978399b852a015ab53 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Mon, 21 May 2007 23:45:38 +0900 Subject: [PATCH] [MIPS] Fix warning by moving do_default_vi into CONFIG_CPU_MIPSR2_SRS This fixes the warning: arch/mips/kernel/traps.c:931: warning: 'do_default_vi' defined but not used Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/kernel/traps.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 200de027f3..3f58b6ac13 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -927,12 +927,6 @@ asmlinkage void do_reserved(struct pt_regs *regs) (regs->cp0_cause & 0x7f) >> 2); } -static asmlinkage void do_default_vi(void) -{ - show_regs(get_irq_regs()); - panic("Caught unexpected vectored interrupt."); -} - /* * Some MIPS CPUs can enable/disable for cache parity detection, but do * it different ways. @@ -1128,6 +1122,12 @@ void mips_srs_free(int set) clear_bit(set, &sr->sr_allocated); } +static asmlinkage void do_default_vi(void) +{ + show_regs(get_irq_regs()); + panic("Caught unexpected vectored interrupt."); +} + static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) { unsigned long handler; -- 2.39.5