From 594a9dfae7113d9601b2c353754c40d0b7e00a03 Mon Sep 17 00:00:00 2001 From: Michael Chan Date: Tue, 28 Aug 2007 15:39:42 -0700 Subject: [PATCH] [BNX2]: Add write posting comment. Add comment to explain why we cannot read back after chip reset before delaying. Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/bnx2.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 00918602ba..854d80c330 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c @@ -3934,6 +3934,10 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) /* Chip reset. */ REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); + /* Reading back any register after chip reset will hang the + * bus on 5706 A0 and A1. The msleep below provides plenty + * of margin for write posting. + */ if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || (CHIP_ID(bp) == CHIP_ID_5706_A1)) msleep(20); -- 2.39.5