From 4c4925c1f4ccd72002957c3e73b4f117f2bcf712 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 11 Jun 2008 12:40:13 -0400 Subject: [PATCH] [ARM] fix cache alignment code in memset.S This code is currently disabled, which explains why no one was affected. Signed-off-by: Nicolas Pitre Signed-off-by: Lennert Buytenhek --- arch/arm/lib/memmove.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S index ef7fddc14a..018522c3ff 100644 --- a/arch/arm/lib/memmove.S +++ b/arch/arm/lib/memmove.S @@ -60,6 +60,7 @@ ENTRY(memmove) CALGN( bcs 2f ) CALGN( adr r4, 6f ) CALGN( subs r2, r2, ip ) @ C is set here + CALGN( rsb ip, ip, #32 ) CALGN( add pc, r4, ip ) PLD( pld [r1, #-4] ) @@ -139,7 +140,6 @@ ENTRY(memmove) blt 14f CALGN( ands ip, r1, #31 ) - CALGN( rsb ip, ip, #32 ) CALGN( sbcnes r4, ip, r2 ) @ C is always set here CALGN( subcc r2, r2, ip ) CALGN( bcc 15f ) -- 2.39.5