From 45828b812ddb608ddf83eff11601f62b726d13ab Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 7 May 2008 11:41:26 +0800 Subject: [PATCH] Blackfin Serial Driver: abstract away DLAB differences into header Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- drivers/serial/bfin_5xx.c | 40 ++++--------------- .../asm-blackfin/mach-bf527/bfin_serial_5xx.h | 3 ++ .../asm-blackfin/mach-bf533/bfin_serial_5xx.h | 3 ++ .../asm-blackfin/mach-bf537/bfin_serial_5xx.h | 3 ++ .../asm-blackfin/mach-bf548/bfin_serial_5xx.h | 3 ++ .../asm-blackfin/mach-bf561/bfin_serial_5xx.h | 3 ++ 6 files changed, 22 insertions(+), 33 deletions(-) diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c index 869c99aa77..d6b4ead693 100644 --- a/drivers/serial/bfin_5xx.c +++ b/drivers/serial/bfin_5xx.c @@ -136,10 +136,7 @@ void kgdb_put_debug_char(int chr) SSYNC(); } -#ifndef CONFIG_BF54x - UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB)); - SSYNC(); -#endif + UART_CLEAR_DLAB(uart); UART_PUT_CHAR(uart, (unsigned char)chr); SSYNC(); } @@ -158,10 +155,7 @@ int kgdb_get_debug_char(void) while(!(UART_GET_LSR(uart) & DR)) { SSYNC(); } -#ifndef CONFIG_BF54x - UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB)); - SSYNC(); -#endif + UART_CLEAR_DLAB(uart); chr = UART_GET_CHAR(uart); SSYNC(); @@ -764,26 +758,15 @@ bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, UART_PUT_IER(uart, 0); #endif -#ifndef CONFIG_BF54x /* Set DLAB in LCR to Access DLL and DLH */ - val = UART_GET_LCR(uart); - val |= DLAB; - UART_PUT_LCR(uart, val); - SSYNC(); -#endif + UART_SET_DLAB(uart); UART_PUT_DLL(uart, quot & 0xFF); - SSYNC(); UART_PUT_DLH(uart, (quot >> 8) & 0xFF); SSYNC(); -#ifndef CONFIG_BF54x /* Clear DLAB in LCR to Access THR RBR IER */ - val = UART_GET_LCR(uart); - val &= ~DLAB; - UART_PUT_LCR(uart, val); - SSYNC(); -#endif + UART_CLEAR_DLAB(uart); UART_PUT_LCR(uart, lcr); @@ -946,8 +929,7 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, status = UART_GET_IER(uart) & (ERBFI | ETBEI); if (status == (ERBFI | ETBEI)) { /* ok, the port was enabled */ - unsigned short lcr, val; - unsigned short dlh, dll; + u16 lcr, dlh, dll; lcr = UART_GET_LCR(uart); @@ -964,22 +946,14 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, case 2: *bits = 7; break; case 3: *bits = 8; break; } -#ifndef CONFIG_BF54x /* Set DLAB in LCR to Access DLL and DLH */ - val = UART_GET_LCR(uart); - val |= DLAB; - UART_PUT_LCR(uart, val); -#endif + UART_SET_DLAB(uart); dll = UART_GET_DLL(uart); dlh = UART_GET_DLH(uart); -#ifndef CONFIG_BF54x /* Clear DLAB in LCR to Access THR RBR IER */ - val = UART_GET_LCR(uart); - val &= ~DLAB; - UART_PUT_LCR(uart, val); -#endif + UART_CLEAR_DLAB(uart); *baud = get_sclk() / (16*(dll | dlh << 8)); } diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h index 1bbfc2d75b..26e3c8076b 100644 --- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h @@ -50,6 +50,9 @@ #define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) #define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) +#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) +#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) + #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h index d22f052d6c..d016603b66 100644 --- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h @@ -50,6 +50,9 @@ #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) +#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) +#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) + #ifdef CONFIG_BFIN_UART0_CTSRTS # define CONFIG_SERIAL_BFIN_CTSRTS # ifndef CONFIG_UART0_CTS_PIN diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h index ae2362c0bf..f79d1a0e91 100644 --- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h @@ -50,6 +50,9 @@ #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) +#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) +#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) + #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index 6547027cd3..5eb46a77d9 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -54,6 +54,9 @@ #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) #define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v) +#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */ +#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */ + #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h index c209f0df47..7a96287692 100644 --- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h @@ -50,6 +50,9 @@ #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) +#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) +#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) + #ifdef CONFIG_BFIN_UART0_CTSRTS # define CONFIG_SERIAL_BFIN_CTSRTS # ifndef CONFIG_UART0_CTS_PIN -- 2.39.5