From 3c7d9c81e1302c244180e62999a08ca95b175cf5 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 16 Apr 2008 00:15:20 +0100 Subject: [PATCH] [ARM] 4987/1: S3C24XX: Ensure watchdog reset initiated from cached code. There seems to be some problem with at-least the S3C2440 and bus traffic during an reset. It is unlikely, but still possible that the system will hang in such a way that the watchdog cannot get the system out of the state it is in. Change to making the code that calls the watchdog reset run from cached memory so that instruction fetches have quiesced before the watchdog fires. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/plat-s3c24xx/cpu.c | 27 +++++++++ include/asm-arm/arch-s3c2410/system-reset.h | 64 +++++++++++++++++++++ include/asm-arm/arch-s3c2410/system.h | 46 +-------------- 3 files changed, 92 insertions(+), 45 deletions(-) create mode 100644 include/asm-arm/arch-s3c2410/system-reset.h diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index f513ab083b..f5699cadb0 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c @@ -28,15 +28,19 @@ #include #include #include +#include #include #include #include #include +#include #include #include +#include + #include #include @@ -203,6 +207,27 @@ static unsigned long s3c24xx_read_idcode_v4(void) #endif } +/* Hook for arm_pm_restart to ensure we execute the reset code + * with the caches enabled. It seems at least the S3C2440 has a problem + * resetting if there is bus activity interrupted by the reset. + */ +static void s3c24xx_pm_restart(char mode) +{ + if (mode != 's') { + unsigned long flags; + + local_irq_save(flags); + __cpuc_flush_kern_all(); + __cpuc_flush_user_all(); + + arch_reset(mode); + local_irq_restore(flags); + } + + /* fallback, or unhandled */ + arm_machine_restart(mode); +} + void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) { unsigned long idcode = 0x0; @@ -230,6 +255,8 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) panic("Unsupported S3C24XX CPU"); } + arm_pm_restart = s3c24xx_pm_restart; + (cpu->map_io)(mach_desc, size); } diff --git a/include/asm-arm/arch-s3c2410/system-reset.h b/include/asm-arm/arch-s3c2410/system-reset.h new file mode 100644 index 0000000000..1615bce0c0 --- /dev/null +++ b/include/asm-arm/arch-s3c2410/system-reset.h @@ -0,0 +1,64 @@ +/* linux/include/asm-arm/arch-s3c2410/system-reset.h + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks + * + * S3C2410 - System define for arch_reset() function + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include + +#include +#include + +#include +#include + +extern void (*s3c24xx_reset_hook)(void); + +static void +arch_reset(char mode) +{ + struct clk *wdtclk; + + if (mode == 's') { + cpu_reset(0); + } + + if (s3c24xx_reset_hook) + s3c24xx_reset_hook(); + + printk("arch_reset: attempting watchdog reset\n"); + + __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ + + wdtclk = clk_get(NULL, "watchdog"); + if (!IS_ERR(wdtclk)) { + clk_enable(wdtclk); + } else + printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); + + /* put initial values into count and data */ + __raw_writel(0x80, S3C2410_WTCNT); + __raw_writel(0x80, S3C2410_WTDAT); + + /* set the watchdog to go and reset... */ + __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | + S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); + + /* wait for reset to assert... */ + mdelay(500); + + printk(KERN_ERR "Watchdog reset failed to assert reset\n"); + + /* delay to allow the serial port to show the message */ + mdelay(50); + + /* we'll take a jump through zero as a poor second */ + cpu_reset(0); +} diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h index 14de4e596f..ad258085e5 100644 --- a/include/asm-arm/arch-s3c2410/system.h +++ b/include/asm-arm/arch-s3c2410/system.h @@ -17,12 +17,8 @@ #include #include -#include #include -#include -#include - void (*s3c24xx_idle)(void); void (*s3c24xx_reset_hook)(void); @@ -59,44 +55,4 @@ static void arch_idle(void) s3c24xx_default_idle(); } -static void -arch_reset(char mode) -{ - struct clk *wdtclk; - - if (mode == 's') { - cpu_reset(0); - } - - if (s3c24xx_reset_hook) - s3c24xx_reset_hook(); - - printk("arch_reset: attempting watchdog reset\n"); - - __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ - - wdtclk = clk_get(NULL, "watchdog"); - if (!IS_ERR(wdtclk)) { - clk_enable(wdtclk); - } else - printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); - - /* put initial values into count and data */ - __raw_writel(0x80, S3C2410_WTCNT); - __raw_writel(0x80, S3C2410_WTDAT); - - /* set the watchdog to go and reset... */ - __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | - S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); - - /* wait for reset to assert... */ - mdelay(500); - - printk(KERN_ERR "Watchdog reset failed to assert reset\n"); - - /* delay to allow the serial port to show the message */ - mdelay(50); - - /* we'll take a jump through zero as a poor second */ - cpu_reset(0); -} +#include -- 2.39.5