From 093d0faf57e59feee224217273f944e10e4e3562 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 11 Jun 2007 17:17:14 +0200 Subject: [PATCH] [AVR32] Define ARCH_KMALLOC_MINALIGN to L1_CACHE_BYTES This allows SLUB debugging to be used without fear of messing up DMA transfers. SPI is one example that easily breaks without this patch. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/cache.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/asm-avr32/cache.h b/include/asm-avr32/cache.h index dabb955f3c..d3cf35ab11 100644 --- a/include/asm-avr32/cache.h +++ b/include/asm-avr32/cache.h @@ -4,6 +4,15 @@ #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +/* + * Memory returned by kmalloc() may be used for DMA, so we must make + * sure that all such allocations are cache aligned. Otherwise, + * unrelated code may cause parts of the buffer to be read into the + * cache before the transfer is done, causing old data to be seen by + * the CPU. + */ +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES + #ifndef __ASSEMBLER__ struct cache_info { unsigned int ways; -- 2.39.5