]> err.no Git - linux-2.6/log
linux-2.6
16 years ago[POWERPC] Xilinx: Update booting-without-of.
Stephen Neuendorffer [Tue, 8 Jan 2008 19:35:07 +0000 (06:35 +1100)]
[POWERPC] Xilinx: Update booting-without-of.

This now better describes what the UBoot device tree generator
actually does.  In particular:

1) Nodes have a label derived from the device name, and a node name
derived from a generic version of the device type, e.g. 'ethernet',
'serial', etc.

2) Usage of compound nodes (representing more than one device in the
same IP) which actually works.  This requires having a valid
compatible node, and all the other things that a bus normally has.
I've chosen 'xlnx,compound' as the bus name to describe these compound
nodes.

In addition, I've clarified some of the language relating to how mhs
nodes should be represent in the device tree.

Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
16 years ago[POWERPC] Xilinx: Add correct compatible list for device tree bus bindings.
Stephen Neuendorffer [Tue, 8 Jan 2008 19:35:06 +0000 (06:35 +1100)]
[POWERPC] Xilinx: Add correct compatible list for device tree bus bindings.

Includes both flavors of plb, opb, dcr, and a pseudo 'compound' bus
for representing compound peripherals containing more than one logical
device.

Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
16 years ago[POWERPC] Xilinx: update compatible list for interrupt controller
Stephen Neuendorffer [Tue, 8 Jan 2008 19:35:04 +0000 (06:35 +1100)]
[POWERPC] Xilinx: update compatible list for interrupt controller

These values now match what is generated by the uboot BSP generator.

Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
16 years agoMerge branch 'for-2.6.25' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/pasemi
Paul Mackerras [Mon, 31 Dec 2007 02:54:13 +0000 (13:54 +1100)]
Merge branch 'for-2.6.25' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/pasemi

16 years agoRevert "[POWERPC] Disable PCI IO/Mem on a device when resources can't be allocated"
Paul Mackerras [Sun, 30 Dec 2007 23:04:15 +0000 (10:04 +1100)]
Revert "[POWERPC] Disable PCI IO/Mem on a device when resources can't be allocated"

This reverts commit 553aa7659bc0e188348f64e978343ed984eb6e56 at Ben H's
request, because it confused IORESOURCE_* flags with command register
bits.

Requested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] Enable CONFIG_PCI_MSI and CONFIG_MD in pasemi_defconfig
Olof Johansson [Fri, 28 Dec 2007 16:41:28 +0000 (10:41 -0600)]
[POWERPC] Enable CONFIG_PCI_MSI and CONFIG_MD in pasemi_defconfig

Enable MSI now that we have an implementation, and enable CONFIG_MD and
the raid options by default as well.

Signed-off-by: Olof Johansson <olof@lixom.net>
16 years ago[POWERPC] pasemi: Distribute interrupts evenly across cpus
Olof Johansson [Fri, 28 Dec 2007 04:16:29 +0000 (22:16 -0600)]
[POWERPC] pasemi: Distribute interrupts evenly across cpus

By default the OpenPIC on PWRficient will bias to one core (since that
will improve changes of the other core being able to stay idle/powered
down). However, this conflicts with most irq load balancing schemes,
since setting an interrupt to be delivered to either core doesn't really
result in the load being shared. It also doesn't work well with the
soft irq disable feature of PPC, since EE will stay on until the first
interrupt is taken while soft disabled.

Set the gconf0 config bit that enables even distribution of interrupts
among the two cores.

Signed-off-by: Olof Johansson <olof@lixom.net>
16 years ago[POWERPC] pasemi: Implement NMI support
Olof Johansson [Thu, 20 Dec 2007 19:11:18 +0000 (13:11 -0600)]
[POWERPC] pasemi: Implement NMI support

Some PWRficient-based boards have a NMI button that's wired up to a GPIO
as interrupt source. By configuring the openpic accordingly, these get
delivered as a machine check with high priority, instead of as an external
interrupt.

The device tree contains a property "nmi-source" in the openpic node
for these systems, and it's the (hwirq) source for the input.

Also, for these interrupts, the IACK is read from another register than
the regular (MCACK instead), but they are EOI'd as usual. So implement
said function for the mpic driver.

Finally, move a couple of external function defines to include/ instead
of local under sysdev. Being able to mask/unmask and eoi directly saves
us from setting up a dummy irq handler that will never be called.

Signed-off-by: Olof Johansson <olof@lixom.net>
16 years ago[POWERPC] 4xx: Update defconfigs
Josh Boyer [Tue, 25 Dec 2007 01:46:29 +0000 (19:46 -0600)]
[POWERPC] 4xx: Update defconfigs

Update the 4xx board defconfigs

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Minor coding style cleanups for 4xx bootwrapper
Josh Boyer [Tue, 25 Dec 2007 01:46:06 +0000 (19:46 -0600)]
[POWERPC] 4xx: Minor coding style cleanups for 4xx bootwrapper

Remove some unneeded braces and make a busy loop more obvious.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Use machine_device_initcall for bus probe
Josh Boyer [Mon, 24 Dec 2007 16:42:02 +0000 (10:42 -0600)]
[POWERPC] 4xx: Use machine_device_initcall for bus probe

Some machine_xx_initcall macros were recently added that check for the machine
type before calling the function.  This converts the 4xx platforms to use those
for bus probing.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] Remove unneeded variable declarations from mpc837x_mds
Josh Boyer [Mon, 24 Dec 2007 15:01:11 +0000 (09:01 -0600)]
[POWERPC] Remove unneeded variable declarations from mpc837x_mds

Remove the declarations for isa_io_base and isa_mem_base as they are declared
in pci-common.c now.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] Conditionally compile e200 and e500 platforms in cputable
Josh Boyer [Mon, 24 Dec 2007 14:44:47 +0000 (08:44 -0600)]
[POWERPC] Conditionally compile e200 and e500 platforms in cputable

The e200 and e500 platforms are separated in various parts of the kernel with
ifdefs, most notably reg_booke.h and traps.c.  The new machine_check rework
requires them to be similarly separated in cputable.c to avoid compile errors.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Mark of_bus structures as __initdata
Josh Boyer [Mon, 24 Dec 2007 14:40:31 +0000 (08:40 -0600)]
[POWERPC] 4xx: Mark of_bus structures as __initdata

Mark the of_device_id structures used to probe the various busses on 4xx
as __initdata.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Update Kilauea, Rainier, and Walnut defconfigs
Josh Boyer [Thu, 20 Dec 2007 15:00:17 +0000 (09:00 -0600)]
[POWERPC] 4xx: Update Kilauea, Rainier, and Walnut defconfigs

Enable PCI support for these eval boards among other things.  Also selects
PCI for Rainier in the Kconfig file.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Makalu defconfig
Stefan Roese [Fri, 21 Dec 2007 07:11:01 +0000 (18:11 +1100)]
[POWERPC] 4xx: Makalu defconfig

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Makalu dts
Stefan Roese [Fri, 21 Dec 2007 07:10:51 +0000 (18:10 +1100)]
[POWERPC] 4xx: Makalu dts

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Add AMCC Makalu board support to platforms/40x
Stefan Roese [Fri, 21 Dec 2007 07:10:36 +0000 (18:10 +1100)]
[POWERPC] 4xx: Add AMCC Makalu board support to platforms/40x

This patch adds basic support for the AMCC Makalu board to arch/powerpc.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Change Kilauea PCIe bus ranges in dts file
Stefan Roese [Sat, 15 Dec 2007 08:10:56 +0000 (19:10 +1100)]
[POWERPC] 4xx: Change Kilauea PCIe bus ranges in dts file

Currently we have some limitations in the 4xx PCIe driver and can't
support all possible PCIe busses. But the current limits in the
dts file are quite low (only 16 busses per RC). This patch increases
the number to 64 per RC.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Add aliases node to 4xx dts files
Stefan Roese [Sat, 15 Dec 2007 07:55:16 +0000 (18:55 +1100)]
[POWERPC] 4xx: Add aliases node to 4xx dts files

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Add PCI entry to 440GRx Rainier DTS.
Valentine Barshak [Fri, 21 Dec 2007 17:22:39 +0000 (04:22 +1100)]
[POWERPC] 4xx: Add PCI entry to 440GRx Rainier DTS.

This adds PCI entry to PowerPC 440GRx Rainier DTS.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: update 440EP(x)/440GR(x) identical PVR issue workaround
Valentine Barshak [Fri, 21 Dec 2007 16:24:02 +0000 (03:24 +1100)]
[POWERPC] 4xx: update 440EP(x)/440GR(x) identical PVR issue workaround

Renaming the CPU nodes with generic names put the CPU model in
the "model" property and thus broke the PowerPC 440EP(x)/440GR(x)
identical PVR workaround. The updates it to use the new model property
for CPU identification.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Rename CPU nodes to avoid dtc incompatibility
Josh Boyer [Thu, 6 Dec 2007 19:20:05 +0000 (13:20 -0600)]
[POWERPC] 4xx: Rename CPU nodes to avoid dtc incompatibility

Recent DTC versions disallow certain special characters in full paths without
being quoted with {}.  That however breaks compatibility with older DTC
versions.  Work around this by renaming the CPU nodes for the 4xx files to a
generic node name, and specify the processor type in the model property of the
CPU node.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Set ibpre for 405EX in 4xx PCIe driver
Stefan Roese [Fri, 7 Dec 2007 09:34:34 +0000 (20:34 +1100)]
[POWERPC] 4xx: Set ibpre for 405EX in 4xx PCIe driver

This patch sets the ibpre flag (Inbound Presence) for the 405EX
in the 4xx PCIe driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Add Kilauea PCIe support to dts and Kconfig
Stefan Roese [Fri, 7 Dec 2007 09:34:26 +0000 (20:34 +1100)]
[POWERPC] 4xx: Add Kilauea PCIe support to dts and Kconfig

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Change Kilauea dts to support new EMAC device tree properties
Stefan Roese [Sat, 1 Dec 2007 10:25:00 +0000 (21:25 +1100)]
[POWERPC] 4xx: Change Kilauea dts to support new EMAC device tree properties

The recent changes from Benjamin Herrenschmidt to the ibm_newemac now
make it possible to support other 4xx variants by just defining the
correct properties in the device tree. In this case of the 405EX we
need to define "has-mdio" in the RGMII node and "has-inverted-stacr-oc"
and "has-new-stacr-staopc" in the EMAC node same as on the 440EPx.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Add 405EX CPU type needed for EMAC support on Kilauea
Stefan Roese [Sat, 1 Dec 2007 10:19:55 +0000 (21:19 +1100)]
[POWERPC] 4xx: Add 405EX CPU type needed for EMAC support on Kilauea

For EMAC support, 405EX needs to be defined to enable the corresponding
EMAC features (IBM_NEW_EMAC_EMAC4, etc.).

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Fix TLB 0 problem with CONFIG_SERIAL_TEXT_DEBUG
Stefan Roese [Tue, 20 Nov 2007 10:19:16 +0000 (21:19 +1100)]
[POWERPC] 4xx: Fix TLB 0 problem with CONFIG_SERIAL_TEXT_DEBUG

Right now TLB entry 0 ist used as UART0 mapping for the early debug
output (via CONFIG_SERIAL_TEXT_DEBUG). This causes problems when many
TLB's get used upon Linux bootup (e.g. while PCIe scanning behind
bridges and/or switches on 440SPe platforms). This will overwrite the
TLB 0 entry and further debug output's may crash/hang the system.

This patch moves the early debug UART0 TLB entry from 0 to 62 as done
in arch/powerpc. This way it is in the "pinned" area and will not get
overwritten. Also the arch/ppc/mm/44x_mmu.c code is now synced with the
newer code from arch/powerpc.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: libfdt and pci fixes for Rainier
Josh Boyer [Thu, 20 Dec 2007 14:55:34 +0000 (08:55 -0600)]
[POWERPC] 4xx: libfdt and pci fixes for Rainier

Update the Rainier wrapper for the libfdt merge and add the pci flags to the
platform file.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Include missing header
Josh Boyer [Fri, 14 Dec 2007 12:36:35 +0000 (06:36 -0600)]
[POWERPC] 4xx: Include missing header

A small error caused a header file to be removed making sequoia support no
longer compile.  Fix it.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 44x: Sequoia and Rainier updates for 2.6.25
Valentine Barshak [Thu, 6 Dec 2007 16:21:12 +0000 (19:21 +0300)]
[POWERPC] 44x: Sequoia and Rainier updates for 2.6.25

PowerPC 440Epx/GRx Sequoia/Rainier updates for 2.6.25

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Fix 440grx setup function to call 440A fixup
Josh Boyer [Tue, 4 Dec 2007 19:02:18 +0000 (13:02 -0600)]
[POWERPC] 4xx: Fix 440grx setup function to call 440A fixup

The mechanism to do the setup for 440A cores changed recently.  This fixes
the 440grx setup function to call __fixup_440A_mcheck.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Add PCI entry to 440EPx Sequoia DTS.
Valentine Barshak [Fri, 21 Dec 2007 16:26:01 +0000 (03:26 +1100)]
[POWERPC] 4xx: Add PCI entry to 440EPx Sequoia DTS.

This adds PCI entry to PowerPC 440EPx Sequoia DTS.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Correct 440GRx machine_check callback
Valentine Barshak [Fri, 21 Dec 2007 16:22:23 +0000 (03:22 +1100)]
[POWERPC] 4xx: Correct 440GRx machine_check callback

Correct the PowerPC 440GRx machine check callback.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: rework UIC cascade irq handling
Valentine Barshak [Thu, 6 Dec 2007 13:48:26 +0000 (00:48 +1100)]
[POWERPC] 4xx: rework UIC cascade irq handling

This is a UIC cascade handler rework to use set_irq_chained_handler() for
cascade, just like othe ppc platforms do. With current implementation we have
additional redirection for irq handler and we call generic_handle_irq twice
(once for the primary uic and the other time for handling cascade interrupt).
This causes Ingo's realtime support patch to stop working on 4xx.

Not sure of any other possible problems though, but with
set_irq_chained_handler() we can abolish "struct irqaction cascade" from the
chip descriptor and call generic_handle_irq() once, directly for cascade irq.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: make UIC use generic level irq handler
Valentine Barshak [Wed, 14 Nov 2007 14:00:52 +0000 (01:00 +1100)]
[POWERPC] 4xx: make UIC use generic level irq handler

This patch makes PowerPC 4xx UIC use generic level irq handler instead
of a custom handle_uic_irq() function. We ack only edge irqs in mask_ack
callback, since acking a level irq on UIC has no effect if the interrupt
is still asserted by the device, even if the interrupt is already masked.
So, to really de-assert the interrupt we need to de-assert the external
source first *and* ack it on UIC then. The handle_level_irq() function
masks and ack's the interrupt with mask_ack callback prior to calling
the actual ISR and unmasks it at the end. So, to use it with UIC interrupts
we need to ack level irqs in the unmask callback instead, after the ISR
has de-asserted the external interrupt source. Even if we ack the interrupt
that we didn't handle (unmask/ack it at the end of the handler, while
next irq is already pending) it will not de-assert the irq, untill we
de-assert its exteral source.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: 440GRx Rainier default config
Valentine Barshak [Tue, 30 Oct 2007 17:00:49 +0000 (04:00 +1100)]
[POWERPC] 4xx: 440GRx Rainier default config

PowerPC 440GRx Rainier default config.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: 440GRx Rainier board support.
Valentine Barshak [Tue, 30 Oct 2007 16:57:39 +0000 (03:57 +1100)]
[POWERPC] 4xx: 440GRx Rainier board support.

PowerPC 440GRx Rainier board support.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: 440GRx Rainier DTS.
Valentine Barshak [Tue, 30 Oct 2007 16:56:50 +0000 (03:56 +1100)]
[POWERPC] 4xx: 440GRx Rainier DTS.

PowerPC 440GRx Rainier DTS.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: 440GRx Rainier bootwrapper.
Valentine Barshak [Tue, 30 Oct 2007 16:56:06 +0000 (03:56 +1100)]
[POWERPC] 4xx: 440GRx Rainier bootwrapper.

Bootwrapper code for PowerPC 440GRx Rainier board.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: 440EPx Sequoia USB OHCI DTS entry
Valentine Barshak [Mon, 8 Oct 2007 14:26:58 +0000 (00:26 +1000)]
[POWERPC] 4xx: 440EPx Sequoia USB OHCI DTS entry

Add the 440EPx Sequoia USB OHCI device tree entry.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Add 440SPe revA runtime detection to PCIe
Stefan Roese [Fri, 21 Dec 2007 04:39:38 +0000 (15:39 +1100)]
[POWERPC] 4xx: Add 440SPe revA runtime detection to PCIe

This patch adds runtime detection of the 440SPe revision A chips. These
chips are equipped with a slighly different PCIe core and need special/
different initialization. The compatible node is changed to
"plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that
can be equipped with both PPC revisions like the AMCC Yucca.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] pci32: 4xx embedded platforms want to reassign all PCI resources
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:37 +0000 (15:39 +1100)]
[POWERPC] pci32: 4xx embedded platforms want to reassign all PCI resources

This makes 4xx embedded platforms re-assign all PCI resources as we
pretty much never care about what the various firmwares have done on
these, it's generally not compatible with the way the kernel will map
the bridges.

We still need to also enable bus renumbering on some of them, but I
will do that from a separate patch after I've fixed 4xx PCIe to handle
all bus numbers.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: PCI-E Link setup improvements
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:36 +0000 (15:39 +1100)]
[POWERPC] 4xx: PCI-E Link setup improvements

This improves the way the 4xx PCI-E code handles checking for a link
and adds explicit testing of CRS result codes on config space accesses.

This should make it more reliable.

Also, bridges with no link are now still created, though config space
accesses beyond the root complex are filtered. This is one step toward
eventually supporting hotplug.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: remove bogus "ranges" property in Bamboo EBC node
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:35 +0000 (15:39 +1100)]
[POWERPC] 4xx: remove bogus "ranges" property in Bamboo EBC node

This removes a bogus empty "ranges" property in the EBC device node
of the Bamboo board device-tree.

The "ranges" property should be created by the wrapper code when it is
implemented.  Until then, remove the empty property since it incorrectly
implies that there is a 1:1 address mapping between the EBC and the OPB.

This also fixes a warning from newer DTCs.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Base support for 440SPe "Katmai" eval board
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:34 +0000 (15:39 +1100)]
[POWERPC] 4xx: Base support for 440SPe "Katmai" eval board

This adds base support for the Katmai board, including PCI-X and
PCI-Express (but no RTC, nvram, etc... yet).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Rework clock probing in boot wrapper
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:33 +0000 (15:39 +1100)]
[POWERPC] 4xx: Rework clock probing in boot wrapper

This reworks the boot wrapper library function that probes
the chip clocks. Better separate the base function that is
used on 440GX,SPe,EP,... from the uart fixups as those need
different device-tree path on different processors.

Also, rework the function itself based on the arch/ppc code
from Eugene Surovegin which I find more readable, and which
handles one more bypass case. Also handle the subtle difference
between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived
from the PLB clock while on the later, it's derived from the OPB.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Add CPR0 accessors to boot wrapper
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:32 +0000 (15:39 +1100)]
[POWERPC] 4xx: Add CPR0 accessors to boot wrapper

This adds macros to the boot wrapper to access the CPR
registers from the boot wrappers.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Add mfspr/mtspr inline macros to 4xx bootwrapper
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:32 +0000 (15:39 +1100)]
[POWERPC] 4xx: Add mfspr/mtspr inline macros to 4xx bootwrapper

The 4xx bootwrapper occasionally needs to access SPR registers,
this adds mfspr/mtspr wrappers to it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Adds decoding of 440SPE memory size to boot wrapper library
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:31 +0000 (15:39 +1100)]
[POWERPC] 4xx: Adds decoding of 440SPE memory size to boot wrapper library

This adds a function to the bootwrapper 4xx library to decode memory
size on 440SPE processors.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Wire up 440EP USB controller support to Bamboo board
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:30 +0000 (15:39 +1100)]
[POWERPC] 4xx: Wire up 440EP USB controller support to Bamboo board

This adds the definition of the on-chip OHCI controller to the
Bamboo board's device-tree. This is enough to get it probed and
working, though a separate patch fixing a bug in the OHCI driver
is needed to make it reliable.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Wire up PCI on Bamboo board
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:29 +0000 (15:39 +1100)]
[POWERPC] 4xx: Wire up PCI on Bamboo board

This adds the device-tree bits & call to ppc4xx_pci_find_bridges()
to make PCI work on the Bamboo board

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Base support for 440GX Taishan eval board
Hugh Blemings [Fri, 21 Dec 2007 04:39:28 +0000 (15:39 +1100)]
[POWERPC] 4xx: Base support for 440GX Taishan eval board

This patch adds base support for the AMCC Taishan 440GX evaluation
board.

Signed-off-by: Hugh Blemings <hugh@blemings.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Add PCI to Walnut platform
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:28 +0000 (15:39 +1100)]
[POWERPC] 4xx: Add PCI to Walnut platform

This wires up the 4xx PCI support & device-tree bits for the
405GP based Walnut platform.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: EP405 boards support for arch/powerpc
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:26 +0000 (15:39 +1100)]
[POWERPC] 4xx: EP405 boards support for arch/powerpc

Brings EP405 support to arch/powerpc. The IRQ routing for the CPLD
comes from a device-tree property, PCI is working to the point where
I can see the video card, USB device, and south bridge.

This should work with both EP405 and EP405PC.

I've not totally figured out how IRQs are wired on this hardware
though, thus at this stage, expect only USB interrupts working,
pretty much the same as what arch/ppc did.

Also, the flash, nvram, rtc and temp control still have to be wired.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Add early udbg support for 40x processors
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:26 +0000 (15:39 +1100)]
[POWERPC] 4xx: Add early udbg support for 40x processors

This adds some basic real mode based early udbg support for 40x
in order to debug things more easily

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: PCI support for Ebony board
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:25 +0000 (15:39 +1100)]
[POWERPC] 4xx: PCI support for Ebony board

This wires up the 4xx PCI support & device tree bits for
440GP based Ebony platform.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: PLB to PCI Express support
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:24 +0000 (15:39 +1100)]
[POWERPC] 4xx: PLB to PCI Express support

This adds to the previous 2 patches the support for the 4xx PCI Express
cells as found in the 440SPe revA, revB and 405EX.

Unfortunately, due to significant differences between these, and other
interesting "features" of those pieces of HW, the code isn't as simple
as it is for PCI and PCI-X and some of the functions differ significantly
between the 3 implementations. Thus, not only this code can only support
those 3 implementations for now and will refuse to operate on any other,
but there are added ifdef's to avoid the bloat of building a fairly large
amount of code on platforms that don't need it.

Also, this code currently only supports fully initializing root complex
nodes, not endpoint. Some more code will have to be lifted from the
arch/ppc implementation to add the endpoint support, though it's mostly
differences in memory mapping, and the question on how to represent
endpoint mode PCI in the device-tree is thus open.

Many thanks to Stefan Roese for testing & fixing up the 405EX bits !

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: PLB to PCI 2.x support
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:23 +0000 (15:39 +1100)]
[POWERPC] 4xx: PLB to PCI 2.x support

This adds to the previous patch the support for the 4xx PCI 2.x
bridges.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: PLB to PCI-X support
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:22 +0000 (15:39 +1100)]
[POWERPC] 4xx: PLB to PCI-X support

This adds base support code for the 4xx PCI-X bridge. It also provides
placeholders for the PCI and PCI-E version but they aren't supported
with this patch.

The bridges are configured based on device-tree properties.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] 4xx: Improve support for 4xx indirect DCRs
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:22 +0000 (15:39 +1100)]
[POWERPC] 4xx: Improve support for 4xx indirect DCRs

Accessing indirect DCRs is done via a pair of address/data DCRs.

Such accesses are thus inherently racy, vs. interrupts, preemption
and possibly SMP if 4xx SMP cores are ever used.

This updates the mfdcri/mtdcri macros in dcr-native.h (which were
so far unused) to use a spinlock.

In addition, add some common definitions to a new dcr-regs.h file.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years ago[POWERPC] Reworking machine check handling and Fix 440/440A
Benjamin Herrenschmidt [Fri, 21 Dec 2007 04:39:21 +0000 (15:39 +1100)]
[POWERPC] Reworking machine check handling and Fix 440/440A

This adds a cputable function pointer for the CPU-side machine
check handling. The semantic is still the same as the old one,
the one in ppc_md. overrides the one in cputable, though
ultimately we'll want to change that so the CPU gets first.

This removes CONFIG_440A which was a problem for multiplatform
kernels and instead fixes up the IVOR at runtime from a setup_cpu
function. The "A" version of the machine check also tweaks the
regs->trap value to differenciate the 2 versions at the C level.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
16 years agoMerge branch 'linux-2.6'
Paul Mackerras [Fri, 21 Dec 2007 11:21:08 +0000 (22:21 +1100)]
Merge branch 'linux-2.6'

16 years ago[POWERPC] Make non-PCI build work again
Stephen Rothwell [Fri, 21 Dec 2007 04:37:07 +0000 (15:37 +1100)]
[POWERPC] Make non-PCI build work again

Maple and pasemi both require PCI as does CONFIG_OF_PLATFORM_PCI.
The default setting of CONFIG_ISA_DMA_API is set to match the protection
around the relevant routines in asm/dma.h.

I also had to remove the PMAC platform from the combined build.  The
precis is that to build a 64 bit kernel with no PCI, you can only include
pSeries and iSeries.

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] Pointers marked as __iomem do not need to be volatile
Stephen Rothwell [Fri, 21 Dec 2007 04:23:48 +0000 (15:23 +1100)]
[POWERPC] Pointers marked as __iomem do not need to be volatile

Fixes this warning:

arch/powerpc/platforms/powermac/pci.c: In function 'u3_ht_cfg_access':
arch/powerpc/platforms/powermac/pci.c:354: warning: return discards qualifiers from pointer target type
arch/powerpc/platforms/powermac/pci.c:358: warning: return discards qualifiers from pointer target type

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] Constify the of_device_id passed to of_platform_bus_probe
Stephen Rothwell [Fri, 21 Dec 2007 04:21:51 +0000 (15:21 +1100)]
[POWERPC] Constify the of_device_id passed to of_platform_bus_probe

This will allow us to declare const all the statically declared arrrays
of these.

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] The builtin matches for ibmebus.c can be __initdata
Stephen Rothwell [Fri, 21 Dec 2007 04:19:59 +0000 (15:19 +1100)]
[POWERPC] The builtin matches for ibmebus.c can be __initdata

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] Add EHEA and EHCA as modules in the ppc64_defconfig
Stephen Rothwell [Fri, 21 Dec 2007 03:54:59 +0000 (14:54 +1100)]
[POWERPC] Add EHEA and EHCA as modules in the ppc64_defconfig

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] Fix possible NULL deref in ppc32 PCI
Benjamin Herrenschmidt [Fri, 21 Dec 2007 03:53:27 +0000 (14:53 +1100)]
[POWERPC] Fix possible NULL deref in ppc32 PCI

The 32-bit PCI code tests if "bus" is non-NULL after calling
pci_scan_bus_parented() in one place but not another before
dereferencing it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] Fix for via-pmu based backlight control
Benjamin Herrenschmidt [Thu, 20 Dec 2007 04:00:21 +0000 (15:00 +1100)]
[POWERPC] Fix for via-pmu based backlight control

This fixes a few issues with via-pmu based backlight control.

First, it fixes a sign problem with the setup of the backlight
curve since the `range' value there -can- (and will) go negative.

Then, it reworks the interaction between this and the via-pmu sleep
code to properly restore backlight on wakeup from sleep.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] Implement arch disable/enable irq hooks.
Scott Wood [Wed, 12 Dec 2007 17:35:19 +0000 (04:35 +1100)]
[POWERPC] Implement arch disable/enable irq hooks.

These hooks ensure that a decrementer interrupt is not pending when
suspending; otherwise, problems may occur on 6xx/7xx/7xxx-based
systems (except for powermacs, which use a separate suspend path).
For example, with deep sleep on the 831x, a pending decrementer will
cause a system freeze because the SoC thinks the decrementer interrupt
would have woken the system, but the core must have interrupts
disabled due to the setup required for deep sleep.

Changed via-pmu.c to use the new ppc_md hooks, and made the arch_*
functions call the generic_* functions unconditionally.  -- paulus

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: Don't leak kernel stack through an empty {i,m}box_info read
Jeremy Kerr [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: Don't leak kernel stack through an empty {i,m}box_info read

Based on an original patch from Arnd Bergmann
<arnd.bergmann@de.ibm.com>

If there's no entry in the mailbox, then a read on the _info file will
return data from an uninitialised variable.

This change returns EOF if there's no mailbox info available instead.

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: DMA Restart after SIGSEGV
Andre Detsch [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: DMA Restart after SIGSEGV

This fixes the behavior of spufs when a spu tries a DMA operation
based on a wrong / unavailable address.

Instead of just generating a SIGBUS signal, spufs now
generates a SIGSEGV signal and restarts the problematic DMA operation
after the execution of the application's signal handler.  This allows
applications to employ user-level paging systems.

Although the restart_dma function is called before the application's
signal handler, the operation is not actually performed at this time,
since the spu context is already stopped.  The operation only takes
place when spu_run is restarted (which happens automatically).

Signed-off-by: Andre Detsch <adetsch@br.ibm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: Use separate timer for /proc/spu_loadavg calculation
Aegis Lin [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: Use separate timer for /proc/spu_loadavg calculation

The original spusched_timer was designed to take effect only when
a context is waiting in the runqueue.

This change adds an additional lower-freq timer has been added to
purely handle the spu_load updates. The new timer will be triggered
per LOAD_FREQ ticks.

Signed-off-by: Aegis Lin <aegislin@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: make state_mutex interruptible
Christoph Hellwig [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: make state_mutex interruptible

Make most places that use spu_acquire/spu_acquire_saved interruptible,
this allows getting out of the spufs code when e.g. pressing ctrl+c.
There are a few places where we get called e.g. from spufs teardown
routines were we can't simply err out so these are left with a comment.
For now I've also not touched the poll routines because it's open what
libspe would expect in terms of interrupted system calls.

Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: add enchanced simple attr macros
Christoph Hellwig [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: add enchanced simple attr macros

The simple attr macros currently used by spufs can't deal with the
handlers returning errors, which is required to make the state_mutex
interruptible.  This adds a local copy that allows for an error
return from the get/set handlers.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: decouple spu scheduler from spufs_spu_run (asynchronous scheduling)
Luke Browning [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: decouple spu scheduler from spufs_spu_run (asynchronous scheduling)

Change spufs_spu_run so that the context is queued directly to the
scheduler and the controlling thread advances directly to spufs_wait()
for spe errors and exceptions.

nosched contexts are treated the same as before.

Fixes from Christoph Hellwig <hch@lst.de>

Signed-off-by: Luke Browning <lukebr@linux.vnet.ibm.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: don't set reserved bits in spu interrupt status
Masato Noguchi [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: don't set reserved bits in spu interrupt status

This changes the spu context switch code to not write to reserved bits
of spu interrupt status register.
The architecture book says the reserved fields should be set to zero.

Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: spu_find_victim may choose wrong victim
Luke Browning [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: spu_find_victim may choose wrong victim

Need to re-check priority after dropping lock.  Otherwise, a
more favored context may be preempted.

Signed-off-by: Luke Browning <lukebr@linux.vnet.ibm.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: reorganize spu_run_init
Luke Browning [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: reorganize spu_run_init

This cleans up spu_run_init so that it does all of the spu
initialization for spufs_run_spu.  It initializes the spu context as
much as possible before it activates the spu and writes the runcntl
register.

Signed-off-by: Luke Browning <lukebr@linux.vnet.ibm.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: rework class 0 and 1 interrupt handling
Jeremy Kerr [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: rework class 0 and 1 interrupt handling

Based on original patches from
 Arnd Bergmann <arnd.bergman@de.ibm.com>; and
 Luke Browning <lukebr@linux.vnet.ibm.com>

Currently, spu contexts need to be loaded to the SPU in order to take
class 0 and class 1 exceptions.

This change makes the actual interrupt-handlers much simpler (ie,
set the exception information in the context save area), and defers the
handling code to the spufs_handle_class[01] functions, called from
spufs_run_spu.

This should improve the concurrency of the spu scheduling leading to
greater SPU utilization when SPUs are overcommited.

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: use #defines for SPU class [012] exception status
Jeremy Kerr [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: use #defines for SPU class [012] exception status

Add a few #defines for the class 0, 1 and 2 interrupt status bits, and
use them instead of magic numbers when we're setting or checking for
these interrupts.

Also, add a #define for the class 2 mailbox threshold interrupt mask.

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: fix incorrect interrupt status clearing in backing mbox stat poll
Jeremy Kerr [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: fix incorrect interrupt status clearing in backing mbox stat poll

When doing a poll on the mbox stat file of a swapped-out context, we
clear the class 0 interrupt status, rather than the class 2 interrupt
status.

This change corrects the poll operation to clear the correct interrupt.

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: add backing ops for privcntl register
Luke Browning [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: add backing ops for privcntl register

This change encapsulates the spu_privcntl_RW register so that it can
be written through backing ops.  This is necessary so that spu contexts
can be initialized and queued to the scheduler in spufs_run_spu.

Signed-off-by: Luke Browning <lukebr@linux.vnet.ibm.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: block fault handlers in spu_acquire_runnable
Arnd Bergmann [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: block fault handlers in spu_acquire_runnable

This change disables the logic that faults-in spu contexts under the
covers from the page fault handler.  When a fault requires a runnable
context, the handler will block until the context is scheduled by
other means.

Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: move fault, lscsa_alloc and switch code to spufs module
Jeremy Kerr [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: move fault, lscsa_alloc and switch code to spufs module

Currently, part of the spufs code (switch.o, lscsa_alloc.o and fault.o)
is compiled directly into the kernel.

This change moves these components of spufs into the kernel.

The lscsa and switch objects are fairly straightforward to move in.

For the fault.o module, we split the fault-handling code into two
parts: a/p/p/c/spu_fault.c and a/p/p/c/spufs/fault.c. The former is for
the in-kernel spu_handle_mm_fault function, and we move the rest of the
fault-handling code into spufs.

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] spufs: fix typos in sched.c comments
Julio M. Merino Vidal [Thu, 20 Dec 2007 07:39:59 +0000 (16:39 +0900)]
[POWERPC] spufs: fix typos in sched.c comments

Fix a few typos in the spufs scheduler comments

Signed-off-by: Julio M. Merino Vidal <jmerino@ac.upc.edu>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] cell: wrap master run control bit
Masato Noguchi [Wed, 5 Dec 2007 02:49:31 +0000 (13:49 +1100)]
[POWERPC] cell: wrap master run control bit

Add platform specific SPU run control routines to the spufs.  The current
spufs implementation uses the SPU master run control bit (MFC_SR1[S]) to
control SPE execution, but the PS3 hypervisor does not support the use of
this feature.

This change adds the run control wrapper routies spu_enable_spu() and
spu_disable_spu().  The bare metal routines use the master run control
bit, and the PS3 specific routines use the priv2 run control register.

An outstanding enhancement for the PS3 would be to add a guard to check
for incorrect access to the spu problem state when the spu context is
disabled.  This check could be implemented with a flag added to the spu
context that would inhibit mapping problem state pages, and a routine
to unmap spu problem state pages.  When the spu is enabled with
ps3_enable_spu() the flag would be set allowing pages to be mapped,
and when the spu is disabled with ps3_disable_spu() the flag would be
cleared and mapped problem state pages would be unmapped.

Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com>
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years ago[POWERPC] Optimize counting distinct entries in the relocation sections
Emil Medve [Tue, 13 Nov 2007 16:24:04 +0000 (03:24 +1100)]
[POWERPC] Optimize counting distinct entries in the relocation sections

When a module has relocation sections with tens of thousands of
entries, counting the distinct/unique entries only (i.e. no
duplicates) at load time can take tens of seconds and up to minutes.
The sore point is the count_relocs() function which is called as part
of the architecture specific module loading processing path:

-> load_module() generic
   -> module_frob_arch_sections() arch specific
      -> get_plt_size() 32-bit
      -> get_stubs_size() 64-bit
 -> count_relocs()

Here count_relocs is being called to find out how many distinct
targets of R_PPC_REL24 relocations there are, since each distinct
target needs a PLT entry or a stub created for it.

The previous counting algorithm has O(n^2) complexity.  Basically two
solutions were proposed on the e-mail list: a hash based approach and
a sort based approach.

The hash based approach is the fastest (O(n)) but the has it needs
additional memory and for certain corner cases it could take lots of
memory due to the degeneration of the hash.  One such proposal was
submitted here:

http://ozlabs.org/pipermail/linuxppc-dev/2007-June/037641.html

The sort based approach is slower (O(n * log n + n)) but if the
sorting is done "in place" it doesn't need additional memory.
This has O(n + n * log n) complexity with no additional memory
requirements.

This commit implements the in-place sort option.

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
16 years agoLinux 2.6.24-rc6 v2.6.24-rc6
Linus Torvalds [Fri, 21 Dec 2007 01:25:48 +0000 (17:25 -0800)]
Linux 2.6.24-rc6

16 years agoMerge git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86
Linus Torvalds [Fri, 21 Dec 2007 01:02:37 +0000 (17:02 -0800)]
Merge git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86

* git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86:
  x86: intel_cacheinfo.c: cpu cache info entry for Intel Tolapai
  x86: fix die() to not be preemptible

16 years agoMerge branch 'for-linus' of git://oss.sgi.com:8090/xfs/xfs-2.6
Linus Torvalds [Fri, 21 Dec 2007 01:02:22 +0000 (17:02 -0800)]
Merge branch 'for-linus' of git://oss.sgi.com:8090/xfs/xfs-2.6

* 'for-linus' of git://oss.sgi.com:8090/xfs/xfs-2.6:
  [XFS] Initialise current offset in xfs_file_readdir correctly
  [XFS] Fix mknod regression

16 years ago[XFS] Initialise current offset in xfs_file_readdir correctly
Lachlan McIlroy [Fri, 21 Dec 2007 00:00:23 +0000 (11:00 +1100)]
[XFS] Initialise current offset in xfs_file_readdir correctly

After reading the directory contents into the temporary buffer, we grab
each dirent and pass it to filldir witht eh current offset of the dirent.
The current offset was not being set for the first dirent in the temporary
buffer, which coul dresult in bad offsets being set in the f_pos field
result in looping and duplicate entries being returned from readdir.

SGI-PV: 974905
SGI-Modid: xfs-linux-melb:xfs-kern:30282a

Signed-off-by: David Chinner <dgc@sgi.com>
Signed-off-by: Tim Shimmin <tes@sgi.com>
Signed-off-by: Lachlan McIlroy <lachlan@sgi.com>
16 years ago[XFS] Fix mknod regression
Christoph Hellwig [Thu, 20 Dec 2007 23:58:56 +0000 (10:58 +1100)]
[XFS] Fix mknod regression

This was broken by my '[XFS] simplify xfs_create/mknod/symlink prototype',
which assigned the re-shuffled ondisk dev_t back to the rdev variable in
xfs_vn_mknod. Because of that i_rdev is set to the ondisk dev_t instead of
the linux dev_t later down the function.

Fortunately the fix for it is trivial: we can just remove the assignment
because xfs_revalidate_inode has done the proper job before unlocking the
inode.

SGI-PV: 974873
SGI-Modid: xfs-linux-melb:xfs-kern:30273a

Signed-off-by: Christoph Hellwig <hch@infradead.org>
Signed-off-by: David Chinner <dgc@sgi.com>
Signed-off-by: Lachlan McIlroy <lachlan@sgi.com>
16 years agox86: intel_cacheinfo.c: cpu cache info entry for Intel Tolapai
Jason Gaston [Fri, 21 Dec 2007 00:27:19 +0000 (01:27 +0100)]
x86: intel_cacheinfo.c: cpu cache info entry for Intel Tolapai

This patch adds a cpu cache info entry for the Intel Tolapai cpu.

Signed-off-by: Jason Gaston <jason.d.gaston@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
16 years agox86: fix die() to not be preemptible
Ingo Molnar [Fri, 21 Dec 2007 00:27:19 +0000 (01:27 +0100)]
x86: fix die() to not be preemptible

Andrew "Eagle Eye" Morton noticed that we use raw_local_save_flags()
instead of raw_local_irq_save(flags) in die(). This allows the
preemption of oopsing contexts - which is highly undesirable. It also
causes CONFIG_DEBUG_PREEMPT to complain, as reported by Miles Lane.

this bug was introduced via:

  commit 39743c9ef717fd4f2b5583f010115c5f2482b8ae
  Author: Andi Kleen <ak@suse.de>
  Date:   Fri Oct 19 20:35:03 2007 +0200

      x86: use raw locks during oopses

-               spin_lock_irqsave(&die.lock, flags);
+               __raw_spin_lock(&die.lock);
+               raw_local_save_flags(flags);

that is not a correct open-coding of spin_lock_irqsave(): both the
ordering is wrong (irqs should be disabled _first_), and the wrong
flags-saving API was used.

Signed-off-by: Ingo Molnar <mingo@elte.hu>
16 years agoMerge git://git.kernel.org/pub/scm/linux/kernel/git/mingo/linux-2.6-sched
Linus Torvalds [Thu, 20 Dec 2007 19:53:41 +0000 (11:53 -0800)]
Merge git://git.kernel.org/pub/scm/linux/kernel/git/mingo/linux-2.6-sched

* git://git.kernel.org/pub/scm/linux/kernel/git/mingo/linux-2.6-sched:
  debug: add end-of-oops marker
  sched: rt: account the cpu time during the tick

16 years agoMerge git://git.kernel.org/pub/scm/linux/kernel/git/agk/linux-2.6-dm
Linus Torvalds [Thu, 20 Dec 2007 19:25:22 +0000 (11:25 -0800)]
Merge git://git.kernel.org/pub/scm/linux/kernel/git/agk/linux-2.6-dm

* git://git.kernel.org/pub/scm/linux/kernel/git/agk/linux-2.6-dm:
  dm crypt: use bio_add_page
  dm: merge max_hw_sector
  dm: trigger change uevent on rename
  dm crypt: fix write endio
  dm mpath: hp requires scsi
  dm: table detect io beyond device

16 years agodm crypt: use bio_add_page
Milan Broz [Thu, 13 Dec 2007 14:16:10 +0000 (14:16 +0000)]
dm crypt: use bio_add_page

Fix possible max_phys_segments violation in cloned dm-crypt bio.

In write operation dm-crypt needs to allocate new bio request
and run crypto operation on this clone. Cloned request has always
the same size, but number of physical segments can be increased
and violate max_phys_segments restriction.

This can lead to data corruption and serious hardware malfunction.
This was observed when using XFS over dm-crypt and at least
two HBA controller drivers (arcmsr, cciss) recently.

Fix it by using bio_add_page() call (which tests for other
restrictions too) instead of constructing own biovec.

All versions of dm-crypt are affected by this bug.

Cc: stable@kernel.org
Cc: dm-crypt@saout.de
Signed-off-by: Milan Broz <mbroz@redhat.com>
Signed-off-by: Alasdair G Kergon <agk@redhat.com>
16 years agodm: merge max_hw_sector
Neil Brown [Thu, 13 Dec 2007 14:16:04 +0000 (14:16 +0000)]
dm: merge max_hw_sector

Make sure dm honours max_hw_sectors of underlying devices

  We still have no firm testing evidence in support of this patch but
  believe it may help to resolve some bug reports.  - agk

Signed-off-by: Neil Brown <neilb@suse.de>
Signed-off-by: Alasdair G Kergon <agk@redhat.com>