Nicolas Pitre [Fri, 28 Oct 2005 15:35:46 +0000 (16:35 +0100)]
[ARM] 3035/1: RISCOS compat code fix
Patch from Nicolas Pitre
From: Daniel Jacobowitz <dan@debian.org>
> I also fixed a bug that confused me greatly while trying to debug: one
> SIGILL has long been a SIGSEGV because of some broken RISCOS
> compatibility code.
Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Matt Reimer [Fri, 28 Oct 2005 15:25:02 +0000 (16:25 +0100)]
[ARM] 3029/1: Add HWUART support for PXA 255/26x
Patch from Matt Reimer
Adds support for HWUART on PXA 255 / 26x. This patch originally came from
http://svn.rungie.com/svn/gumstix-buildroot/trunk/sources/kernel-patches/000-gumstix-hwuart.patch
and has been tweaked by me.
Signed-off-by: Matt Reimer <mreimer@vpop.net> Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Todd Poynor [Fri, 28 Oct 2005 15:25:01 +0000 (16:25 +0100)]
[ARM] 2787/2: PXA27x low power modes support
Patch from Todd Poynor
Add symbols for PXA2xx PWRMODE register M field that selects low-power
mode, replace unadorned constants. Honor power mode parameter of
pxa_cpu_suspend(mode), no longer force to 3 (sleep). Full Deep Sleep
low-power mode support for PXA27x is pending generic PM interfaces to
select more than 2 suspend-to-RAM-style power modes, but this is
expected soon. This can be hardcoded in the meantime by replacing the
pxa_cpu_suspend() parameter value. From David Burrage and Todd Poynor.
Try #2 removes one of the register copies and moves the code to save the
pxa_cpu_suspend parameter to immediately surround the call that requires
the parameter value be preserved.
Signed-off-by: Todd Poynor <tpoynor@mvista.com> Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Jon Ringle [Fri, 28 Oct 2005 15:19:37 +0000 (16:19 +0100)]
[ARM] 2918/1: [update] Base port of Comdial MP1000 platfrom
Patch from Jon Ringle
Updated 2898/1 per comments:
- Removed fixup
- Moved code in mach-mp1000/ to mach-clps711x/
- Cleaned up code in mp1000-seprom.c. Eliminated code that displayed the contents of the eeprom
Please comment.
Signed-off-by: Jon Ringle Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Al Viro [Fri, 21 Oct 2005 07:20:48 +0000 (03:20 -0400)]
[PATCH] gfp_t: fs/*
- ->releasepage() annotated (s/int/gfp_t), instances updated
- missing gfp_t in fs/* added
- fixed misannotation from the original sweep caught by bitwise checks:
XFS used __nocast both for gfp_t and for flags used by XFS allocator.
The latter left with unsigned int __nocast; we might want to add a
different type for those but for now let's leave them alone. That,
BTW, is a case when __nocast use had been actively confusing - it had
been used in the same code for two different and similar types, with
no way to catch misuses. Switch of gfp_t to bitwise had caught that
immediately...
One tricky bit is left alone to be dealt with later - mapping->flags is
a mix of gfp_t and error indications. Left alone for now.
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Al Viro [Fri, 21 Oct 2005 06:55:38 +0000 (02:55 -0400)]
[PATCH] gfp_t: infrastructure
Beginning of gfp_t annotations:
- -Wbitwise added to CHECKFLAGS
- old __bitwise renamed to __bitwise__
- __bitwise defined to either __bitwise__ or nothing, depending on
__CHECK_ENDIAN__ being defined
- gfp_t switched from __nocast to __bitwise__
- force cast to gfp_t added to __GFP_... constants
- new helper - gfp_zone(); extracts zone bits out of gfp_t value and casts
the result to int
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Ian Campbell [Fri, 28 Oct 2005 14:26:42 +0000 (15:26 +0100)]
[ARM] 3044/1: Fix sparse warnings about incompatible pointer types for register defined in pxa-regs.h
Patch from Ian Campbell
The sparse warning initially surfaced in sound/arm/pxa2xx-ac97.c
because it was using u32 * variables to hold the unsigned long *
register addresses.
I submitted an ALSA patch for this http://thread.gmane.org/gmane.linux.alsa.devel/27804 issue and it was suggested that it might be preferable to change the register
definitions to use u32.
Most other subarches seem to use u32 for their register type, at least
the ones which use a __REG macro (like the PXA) do. Nico indicated in
the thread above that he wouldn't mind this patch.
Changing the type required fixes for opposite warnings in the pxa2xx usb
gadget code but that was the only new warning introduced on defconfig
or lubbock, mainstone and our own PXA255 boards.
Signed-off-by: Ian Campbell <icampbell@arcom.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
A number of devices have an extra byte on the
end of their areas due to mis-calculating the
.end field of their resources
Signed-off-by: Guillaume GOURAT <guillaume.gourat@nexvision.fr> Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add generic values for the parameters to the
s3c2410_gpio_cfgpin() function, so that a caller
does not need to know the exact constant for
the specified pin.
This is very useful for the case where a driver
is passed a gpio pin number and needs to reconfigure
the pin's function.
Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Nicolas Pitre [Fri, 28 Oct 2005 14:26:40 +0000 (15:26 +0100)]
[ARM] 2930/1: optimized sha1 implementation for ARM
Patch from Nicolas Pitre
Here's an ARM assembly SHA1 implementation to replace the default C
version. It is approximately 50% faster than the generic C version. On
an XScale processor running at 400MHz:
generic C version: 9.8 MB/s
my version: 14.5 MB/s
This code is useful to quite a few callers in the tree:
crypto/sha1.c: sha_transform(sctx->state, sctx->buffer, temp);
crypto/sha1.c: sha_transform(sctx->state, &data[i], temp);
drivers/char/random.c: sha_transform(buf, (__u8 *)r->pool+i, buf + 5);
drivers/char/random.c: sha_transform(buf, (__u8 *)data, buf + 5);
net/ipv4/syncookies.c: sha_transform(tmp + 16, (__u8 *)tmp, tmp + 16 + 5);
Signed-off-by: Nicolas Pitre <nico@cam.org>
Seems to work fine on big-endian as well.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Deepak Saxena [Fri, 28 Oct 2005 14:19:12 +0000 (15:19 +0100)]
[ARM] 3017/1: Add support for 36-bit addresses to create_mapping()
Patch from Deepak Saxena
This patch adds support for 36-bit static mapped I/O. While there
are no platforms in the tree ATM that use it, it has been tested
tested on the IXP2350 NPU and I would like to get the support for
that chipset upstream one piece at a time. There are also other
Intel chipset ports in development that are waiting on this to go
upstream.
The patch replaces the print formats for physical addresses with
%016llx which will create a bit extraneous output on 32-bit systems,
but I think that is cleaner than having #ifdefs, specially since
users will only see the output in error cases.
Depends on 3016/1.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Deepak Saxena [Fri, 28 Oct 2005 14:19:11 +0000 (15:19 +0100)]
[ARM] 3016/1: Replace map_desc.physical with map_desc.pfn
Patch from Deepak Saxena
Convert map_desc.physical to map_desc.pfn. This allows us to add
support for 36-bit addressed physical devices in the static maps
without having to resort to u64 variables.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Fri, 28 Oct 2005 13:54:21 +0000 (14:54 +0100)]
[ARM] 3/4 Rename common oprofile code
The common oprofile code assumes the name "PMU" (from Intel's
performance management unit). This is misleading when we
start adding oprofile support for other machine types which
don't use the same terminology. Call it op_arm_* instead of
pmu_*.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Fri, 28 Oct 2005 13:52:30 +0000 (14:52 +0100)]
[ARM] 2/4 Fix oprofile suspend/resume
The oprofile suspend/resume was missing locking. If we failed
to start oprofile on resume, we still reported that it was
enabled. Instead, disable oprofile on error.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Fri, 28 Oct 2005 13:48:37 +0000 (14:48 +0100)]
[ARM] Re-jig bootmem initialisation
Make ARM independent of the way bootmem operates internally. We
now map each node as we initialise it, and place the bootmem bitmap
inside each node, rather than all in the first node.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Jens Axboe [Fri, 28 Oct 2005 06:30:39 +0000 (08:30 +0200)]
[BLOCK] elevator switch fixes/cleanup
- 100msec sleep is a little excessive, lots of requests can complete
in that timeframe. Use 10msec instead.
- Rename QUEUE_FLAG_BYPASS to QUEUE_FLAG_ELVSWITCH to indicate what
is going on.
Tejun Heo [Fri, 28 Oct 2005 06:29:39 +0000 (08:29 +0200)]
[BLOCK] Reimplement elevator switch
This patch reimplements elevator switch. This patch assumes generic
dispatch queue patchset is applied.
* Each request is tagged with REQ_ELVPRIV flag if it has its elevator
private data set.
* Requests which doesn't have REQ_ELVPRIV flag set never enter
iosched. They are always directly back inserted to dispatch queue.
Of course, elevator_put_req_fn is called only for requests which
have its REQ_ELVPRIV set.
* Request queue maintains the current number of requests which have
its elevator data set (elevator_set_req_fn called) in
q->rq->elvpriv.
* If a request queue has QUEUE_FLAG_BYPASS set, elevator private data
is not allocated for new requests.
To switch to another iosched, we set QUEUE_FLAG_BYPASS and wait until
elvpriv goes to zero; then, we attach the new iosched and clears
QUEUE_FLAG_BYPASS. New implementation is much simpler and main code
paths are less cluttered, IMHO.
projects / linux-2.6 / log