Mark Salazar [Mon, 16 Jan 2006 10:35:40 +0000 (11:35 +0100)]
[ALSA] #4/4 for Zoom Video - add Zoom Video support
Modules: ES18xx driver
Forth of 4 es18xx.c patches culminating in Zoom Video support.
This patch adds Zoom Video support for those chipsets that support it.
Testing:
This work was initially done on the source from the Debian Sarge ALSA
package, then tested
on an ES1879. I could not test the Zoom Video function for an ES1878 or
ES1869.
Patches were created against the Sarge code and then edited to apply
correctly to the
ALSA cvs code. Lastly the patched ALSA cvs code was test for successful
compilation.
No additional testing was done on the ALSA cvs version.
One quirk (noted in my comments below) is that apparently the datasheet
is wrong
for one of the ES1879 Zoom Video 'enable' bits, because
1) if you set this bit it messes up PCM playback (speaker_test play a
lower frequency)
2) even if you don't set this bit Zoom Video still works.
I added a control to toggle the bit on just in case there might be a
version of the
ES1879 that requires it, but I expect noone will need it.
Signed-off-by: Mark Salazar <markTheCoder@justmyself.net> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Mark Salazar [Mon, 16 Jan 2006 10:33:52 +0000 (11:33 +0100)]
[ALSA] #3/4 for Zoom Video - change Hardware Volume interrupt handling
Modules: ES18xx driver
Third of 4 es18xx.c patches culminating in Zoom Video support.
This patch changes the Hardware Volume support to reflect the fact that
not all of the
supported chipsets have seperate registers dedicated to the Hardware
Volume inputs. Although
all the chipsets can generate an HWV interrupt whenever a Hardware
Volume input is received
only those with seperate HWV registers can split the HWV registers from
the Master volume
registers.
Testing:
This work was initially done on the source from the Debian Sarge ALSA
package, then tested
on an ES1879 and an ES1878 machine. Patches were created against the
Sarge code and then edited
to apply correctly to the ALSA cvs code. Lastly the patched ALSA cvs
code was test for
successful compilation. No additional testing was done on the ALSA cvs
version.
Signed-off-by: Mark Salazar <markTheCoder@justmyself.net> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Mark Salazar [Mon, 16 Jan 2006 10:31:14 +0000 (11:31 +0100)]
[ALSA] #2/4 for Zoom Video - resolve number of record sources
Modules: ES18xx driver
Second of 4 es18xx.c patches culminating in Zoom Video support.
This patch changes the 'record source' mux routines to reflect the fact
that not all of the
supported chipsets have 8 possible inputs. Some have 4 and some have 5.
Testing:
This work was initially done on the source from the Debian Sarge ALSA
package, then tested
on an ES1879 and an ES1878 machine. Patches were created against the
Sarge code and then edited
to apply correctly to the ALSA cvs code. Lastly the patched ALSA cvs
code was test for
successful compilation. No additional testing was done on the ALSA cvs
version.
Signed-off-by: Mark Salazar <markTheCoder@justmyself.net> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Mark Salazar [Mon, 16 Jan 2006 10:29:09 +0000 (11:29 +0100)]
[ALSA] #1/4 for Zoom Video - resolve common vs chipset specific mixer controls
Modules: ES18xx driver
First of 4 es18xx.c patches culminating in Zoom Video support.
While adding support for Zoom Video to the es18xx driver I found some of
the mixer controls
were wrong. Since you guys went to the trouble of supplying the
datasheets for the supported
chipsets I did a review of all of them and tried to get es18xx.c to
accurately reflect the
proper mixer controls for each chipset. If the datasheets are wrong then
so are my patches.
This first patch moves some controls from the common-to-all-chipsets array
'snd_es18xx_base_controls' to a chipset-specific array and adds code to
manage that new array.
Also while testing on my ES1878 test machine I discovered it needed a
couple of udelays in
the identify function so those are in this patch as well.
Testing:
This work was initially done on the source from the Debian Sarge ALSA
package, then tested
on an ES1879 and an ES1878 machine. Patches were created against the
Sarge code and then edited
to apply correctly to the ALSA cvs code. Lastly the patched ALSA cvs
code was test for
successful compilation. No additional testing was done on the ALSA cvs
version.
Signed-off-by: Mark Salazar <markTheCoder@justmyself.net> Signed-off-by: Takashi Iwai <tiwai@suse.de>
1) The verbose procfs code for the PCM midlevel and usb audio
can be removed now (more patches will follow).
CONFIG_SND_VERBOSE_PROCFS
2) The PCM OSS plugin system can be also compiled optionaly.
CONFIG_SND_PCM_OSS_PLUGINS
Brent Cook [Tue, 10 Jan 2006 13:27:20 +0000 (14:27 +0100)]
[ALSA] Add support for EDIROL UM-3ex
Modules: USB generic driver
This is my naive attempt at adding ALSA device support. The attached
patch provides support for the EDIROL UM-3ex. This is a 3-port USB midi
interface with a built-in USB hub and the ability to chain 2 other
UM-3x's in a master-slave configuration. I only have one, so I do not
know how this works in practice.
Though this is a 3-port device, I had to throw in that 4th 'Control' interface
to the definition in order to make the 3rd port work. If I set in/out_cables
to 0x000b, a 3rd interface appears on the driver, but it does nothing.
Changing it to 0x000f allows the 3rd interface to work, but of course
interface 4 does not work because it does not exist.
* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: (230 commits)
[SPARC64]: Update defconfig.
[SPARC64]: Fix 2 bugs in huge page support.
[SPARC64]: CONFIG_BLK_DEV_RAM fix
[SPARC64]: Optimized TSB table initialization.
[SPARC64]: Allow CONFIG_MEMORY_HOTPLUG to build.
[SPARC64]: Use SLAB caches for TSB tables.
[SPARC64]: Don't kill the page allocator when growing a TSB.
[SPARC64]: Randomize mm->mmap_base when PF_RANDOMIZE is set.
[SPARC64]: Increase top of 32-bit process stack.
[SPARC64]: Top-down address space allocation for 32-bit tasks.
[SPARC64] bbc_i2c: Fix cpu check and add missing module license.
[SPARC64]: Fix and re-enable dynamic TSB sizing.
[SUNSU]: Fix missing spinlock initialization.
[TG3]: Do not try to access NIC_SRAM_DATA_SIG on Sun parts.
[SPARC64]: First cut at VIS simulator for Niagara.
[SPARC64]: Fix system type in /proc/cpuinfo and remove bogus OBP check.
[SPARC64]: Add SMT scheduling support for Niagara.
[SPARC64]: Fix 32-bit truncation which broke sparsemem.
[SPARC64]: Move over to sparsemem.
[SPARC64]: Fix new context version SMP handling.
...
Linus Torvalds [Mon, 20 Mar 2006 18:32:33 +0000 (10:32 -0800)]
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/shaggy/jfs-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/shaggy/jfs-2.6:
JFS: add uid, gid, and umask mount options
JFS: Take logsync lock before testing mp->lsn
JFS: kzalloc conversion
JFS: Add missing file from fa3241d24cf1182b0ffb6e4d412c3bc2a2ab7bf6
JFS: Use the kthread_ API
JFS: Fix regression. fsck complains if symlinks do not have INLINEEA attribute
JFS: ext2 inode attributes for jfs
JFS: semaphore to mutex conversion.
JFS: make buddy table static
JFS: Add back directory i_size calculations for legacy partitions
Linus Torvalds [Mon, 20 Mar 2006 18:30:31 +0000 (10:30 -0800)]
Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6: (150 commits)
[PATCH] ipw2100: Update version ipw2100 stamp to 1.2.2
[PATCH] ipw2100: move mutex.h include from ipw2100.c to ipw2100.h
[PATCH] ipw2100: semaphore to mutexes conversion
[PATCH] ipw2100: Fix radiotap code gcc warning
[PATCH] ipw2100: add radiotap headers to packtes captured in monitor mode
[PATCH] ipw2x00: expend Copyright to 2006
[PATCH] drivers/net/wireless/ipw2200.c: fix an array overun
[PATCH] ieee80211: Don't update network statistics from off-channel packets.
[PATCH] ipw2200: Update ipw2200 version stamp to 1.1.1
[PATCH] ipw2200: switch to the new ipw2200-fw-3.0 image format
[PATCH] ipw2200: wireless extension sensitivity threshold support
[PATCH] ipw2200: Enables the "slow diversity" algorithm
[PATCH] ipw2200: Set a meaningful silence threshold value
[PATCH] ipw2200: export `debug' module param only if CONFIG_IPW2200_DEBUG
[PATCH] ipw2200: Change debug level for firmware error logging
[PATCH] ipw2200: Filter unsupported channels out in ad-hoc mode
[PATCH] ipw2200: Fix ipw_sw_reset() implementation inconsistent with comment
[PATCH] ipw2200: Fix rf_kill is activated after mode change with 'disable=1'
[PATCH] ipw2200: remove the WPA card associates to non-WPA AP checking
[PATCH] ipw2200: Add signal level to iwlist scan output
...
Linus Torvalds [Mon, 20 Mar 2006 18:28:51 +0000 (10:28 -0800)]
Merge branch 'block-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/block
* 'block-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/block:
[PATCH] fix rmmod problems with elevator attributes, clean them up
[PATCH] elevator_t lifetime rules and sysfs fixes
[PATCH] noise removal: cfq-iosched.c
[PATCH] don't bother with refcounting for cfq_data
[PATCH] fix sysfs interaction and lifetime rules handling for queues
[PATCH] regularize blk_cleanup_queue() use
[PATCH] fix cfq_get_queue()/ioprio_set(2) races
[PATCH] deal with rmmod/put_io_context() races
[PATCH] stop elv_unregister() from rogering other iosched's data, fix locking
[PATCH] stop cfq from pinning queue down
[PATCH] make cfq_exit_queue() prune the cfq_io_context for that queue
[PATCH] fix the exclusion for ioprio_set()
[PATCH] keep sync and async cfq_queue separate
[PATCH] switch to use of ->key to get cfq_data by cfq_io_context
[PATCH] stop leaking cfq_data in cfq_set_request()
[PATCH] fix cfq hash lookups
[PATCH] fix locking in queue_requests_store()
[PATCH] fix double-free in blk_init_queue_node()
[PATCH] don't do exit_io_context() until we know we won't be doing any IO
David S. Miller [Sun, 19 Mar 2006 07:55:11 +0000 (23:55 -0800)]
[SPARC64]: Optimized TSB table initialization.
We only need to write an invalid tag every 16 bytes,
so taking advantage of this can save many instructions
compared to the simple memset() call we make now.
A prefetching implementation is implemented for sun4u
and a block-init store version if implemented for Niagara.
The next trick is to be able to perform an init and
a copy_tsb() in parallel when growing a TSB table.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Fri, 17 Mar 2006 22:41:03 +0000 (14:41 -0800)]
[SPARC64]: Top-down address space allocation for 32-bit tasks.
Currently allocations are very constrained for 32-bit processes.
It grows down-up from 0x70000000 to 0xf0000000 which gives about
2GB of stack + dynamic mmap() space.
So support the top-down method, and we need to override the
generic helper function in order to deal with D-cache coloring.
With these changes I was able to squeeze out a mmap() just over
3.6GB in size in a 32-bit process.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Thu, 16 Mar 2006 10:02:32 +0000 (02:02 -0800)]
[SPARC64]: Fix and re-enable dynamic TSB sizing.
This is good for up to %50 performance improvement of some test cases.
The problem has been the race conditions, and hopefully I've plugged
them all up here.
1) There was a serious race in switch_mm() wrt. lazy TLB
switching to and from kernel threads.
We could erroneously skip a tsb_context_switch() and thus
use a stale TSB across a TSB grow event.
There is a big comment now in that function describing
exactly how it can happen.
2) All code paths that do something with the TSB need to be
guarded with the mm->context.lock spinlock. This makes
page table flushing paths properly synchronize with both
TSB growing and TLB context changes.
3) TSB growing events are moved to the end of successful fault
processing. Previously it was in update_mmu_cache() but
that is deadlock prone. At the end of do_sparc64_fault()
we hold no spinlocks that could deadlock the TSB grow
sequence. We also have dropped the address space semaphore.
While we're here, add prefetching to the copy_tsb() routine
and put it in assembler into the tsb.S file. This piece of
code is quite time critical.
There are some small negative side effects to this code which
can be improved upon. In particular we grab the mm->context.lock
even for the tsb insert done by update_mmu_cache() now and that's
a bit excessive. We can get rid of that locking, and the same
lock taking in flush_tsb_user(), by disabling PSTATE_IE around
the whole operation including the capturing of the tsb pointer
and tsb_nentries value. That would work because anyone growing
the TSB won't free up the old TSB until all cpus respond to the
TSB change cross call.
I'm not quite so confident in that optimization to put it in
right now, but eventually we might be able to and the description
is here for reference.
This code seems very solid now. It passes several parallel GCC
bootstrap builds, and our favorite "nut cruncher" stress test which is
a full "make -j8192" build of a "make allmodconfig" kernel. That puts
about 256 processes on each cpu's run queue, makes lots of process cpu
migrations occur, causes lots of page table and TLB flushing activity,
incurs many context version number changes, and it swaps the machine
real far out to disk even though there is 16GB of ram on this test
system. :-)
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Thu, 9 Mar 2006 00:09:19 +0000 (16:09 -0800)]
[SPARC64]: Add SMT scheduling support for Niagara.
The mapping is a simple "(cpuid >> 2) == core" for now.
Later we'll add more sophisticated code that will walk
the sun4v machine description and figure this out from
there.
We should also add core mappings for jaguar and panther
processors.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Wed, 8 Mar 2006 23:57:03 +0000 (15:57 -0800)]
[SPARC64]: Fix 32-bit truncation which broke sparsemem.
The page->flags manipulations done by the D-cache dirty
state tracking was broken because the constants were not
marked with "UL" to make them 64-bit, which means we were
clobbering the upper 32-bits of page->flags all the time.
This doesn't jive well with sparsemem which stores the
section and indexing information in the top 32-bits of
page->flags.
This is yet another sparc64 bug which has been with us
forever.
While we're here, tidy up some things in bootmem_init()
and paginig_init():
1) Pass min_low_pfn to init_bootmem_node(), it's identical
to (phys_base >> PAGE_SHIFT) but we should use consistent
with the variable names we print in CONFIG_BOOTMEM_DEBUG
2) max_mapnr, although no longer used, was being set
inaccurately, we shouldn't subtract pfn_base any more.
3) All the games with phys_base in the zones_*[] arrays
we pass to free_area_init_node() are no longer necessary.
Thanks to Josh Grebe and Fabbione for the bug reports
and testing. Fix also verified locally on an SB2500
which had a memory layout that triggered the same problem.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Tue, 7 Mar 2006 06:50:44 +0000 (22:50 -0800)]
[SPARC64]: Fix new context version SMP handling.
Don't piggy back the SMP receive signal code to do the
context version change handling.
Instead allocate another fixed PIL number for this
asynchronous cross-call. We can't use smp_call_function()
because this thing is invoked with interrupts disabled
and a few spinlocks held.
Also, fix smp_call_function_mask() to count "cpus" correctly.
There is no guarentee that the local cpu is in the mask
yet that is exactly what this code was assuming.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Tue, 7 Mar 2006 03:59:50 +0000 (19:59 -0800)]
[SPARC64]: Bulletproof MMU context locking.
1) Always spin_lock_init() in init_context(). The caller essentially
clears it out, or copies the mm info from the parent. In both
cases we need to explicitly initialize the spinlock.
2) Always do explicit IRQ disabling while taking mm->context.lock
and ctx_alloc_lock.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Fri, 3 Mar 2006 05:50:47 +0000 (21:50 -0800)]
[SPARC64]: More SUN4V cpu mondo bug fixing.
This cpu mondo sending interface isn't all that easy to
use correctly...
We were clearing out the wrong bits from the "mask" after getting
something other than EOK from the hypervisor.
It turns out the hypervisor can just be resent the same cpu_list[]
array, with the 0xffff "done" entries still in there, and it will do
the right thing.
So don't update or try to rebuild the cpu_list[] array to condense it.
This requires the "forward_progress" check to be done slightly
differently, but this new scheme is less bug prone than what we were
doing before.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Fri, 3 Mar 2006 02:12:27 +0000 (18:12 -0800)]
[SPARC64]: Do not allow mapping pages within 4GB of 64-bit VA hole.
The UltraSPARC T1 manual recommends this because the chip
could instruction prefetch into the VA hole, and this would
also make decoding certain kinds of memory access traps
more difficult (because the chip sign extends certain pieces
of trap state).
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Thu, 2 Mar 2006 06:42:18 +0000 (22:42 -0800)]
[SPARC64]: Fix _PAGE_EXEC handling.
First of all, use the known _PAGE_EXEC_{4U,4V} value instead
of loading _PAGE_EXEC from memory. We either know which one
to use by context, or we can code patch the test.
Next, we need to check executability of a PTE in the generic
TSB miss handler.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Tue, 28 Feb 2006 23:10:26 +0000 (15:10 -0800)]
[SPARC64]: Fix bugs in SUN4V cpu mondo dispatch.
There were several bugs in the SUN4V cpu mondo dispatch code.
In fact, if we ever got a EWOULDBLOCK or other error from
the hypervisor call, we'd potentially send a cpu mondo multiple
times to the same cpu and even worse we could loop until the
timeout resending the same mondo over and over to such cpus.
So let's bulletproof this thing as follows:
1) Implement cpu_mondo_send() and cpu_state() hypervisor calls
in arch/sparc64/kernel/entry.S, add prototypes to asm/hypervisor.h
2) Don't build and update the cpulist using inline functions, this
was causing the cpu mask to not get updated in the caller.
3) Disable interrupts during the entire mondo send, otherwise our
cpu list and/or mondo block could get overwritten if we take
an interrupt and do a cpu mondo send on the current cpu.
4) Check for all possible error return types from the cpu_mondo_send()
hypervisor call. In particular:
HV_EOK) Our work is done, all cpus have received the mondo.
HV_CPUERROR) One or more of the cpus in the cpu list we passed
to the hypervisor are in error state. Use cpu_state()
calls over the entries in the cpu list to see which
ones. Record them in "error_mask" and report this
after we are done sending the mondo to cpus which are
not in error state.
HV_EWOULDBLOCK) We need to keep trying.
Any other error we consider fatal, we report the event and exit
immediately.
5) We only timeout if forward progress is not made. Forward progress
is defined as having at least one cpu get the mondo successfully
in a given cpu_mondo_send() call. Otherwise we bump a counter
and delay a little. If the counter hits a limit, we signal an
error and report the event.
Also, smp_call_function_mask() error handling reports the number
of cpus incorrectly.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Thu, 23 Feb 2006 22:19:28 +0000 (14:19 -0800)]
[SPARC64]: Fix TLB context allocation with SMT style shared TLBs.
The context allocation scheme we use depends upon there being a 1<-->1
mapping from cpu to physical TLB for correctness. Chips like Niagara
break this assumption.
So what we do is notify all cpus with a cross call when the context
version number changes, and if necessary this makes them allocate
a valid context for the address space they are running at the time.
Stress tested with make -j1024, make -j2048, and make -j4096 kernel
builds on a 32-strand, 8 core, T2000 with 16GB of ram.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Thu, 23 Feb 2006 00:20:11 +0000 (16:20 -0800)]
[SPARC64]: Fix %tstate ASI handling in start_thread{,32}()
Niagara helps us find a ancient bug in the sparc64 port :-)
The ASI_* values are plain constant defines, thus signed 32-bit
on sparc64. To put shift this into the regs->tstate value we were
doing or'ing "(ASI_PNF << 24)" into there.
ASI_PNF is 0x82 and shifted left by 24 makes that topmost bit the
sign bit in a 32-bit value. This would get sign extended to 64-bits
and thus corrupt the top-half of the reg->tstate value.
This never caused problems in pre-Niagara cpus because the only thing
up there were the condition code values. But Niagara has the global
register level field, and this all 1's value is illegal there so
Niagara gives an illegal instruction trap due to this bug.
I'm pretty sure this bug is about as old as the sparc64 port itself.
This also points out that we weren't setting ASI_PNF for 32-bit tasks.
We should, so fix that while we're here.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Thu, 23 Feb 2006 00:15:45 +0000 (16:15 -0800)]
[SPARC64]: Drop %gl to 0 before re-enabling PSTATE_IE in rtrap
If we take a window fault, on SUN4V set %gl to zero before we
turn PSTATE_IE back on in %pstate. Otherwise if we take an
interrupt we'll end up with corrupt register state.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Wed, 22 Feb 2006 06:31:11 +0000 (22:31 -0800)]
[SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings.
It can map all of the linear kernel mappings with zero TSB hash
conflicts for systems with 16GB or less ram. In such cases, on
SUN4V, once we load up this TSB the first time with all the
mappings, we never take a linear kernel mapping TLB miss ever
again, the hypervisor handles them all.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Wed, 22 Feb 2006 00:55:23 +0000 (16:55 -0800)]
[SPARC64]: Use sun4v_cpu_idle() in cpu_idle() on SUN4V.
We have to turn off the "polling nrflag" bit when we sleep
the cpu like this, so that we'll get a cross-cpu interrupt
to wake the processor up from the yield.
We also have to disable PSTATE_IE in %pstate around the yield
call and recheck need_resched() in order to avoid any races.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Tue, 21 Feb 2006 00:02:24 +0000 (16:02 -0800)]
[SPARC64]: Handle unimplemented FPU square-root on Niagara.
The math-emu code only expects unfinished fpop traps when
emulating FPU sqrt instructions on pre-Niagara chips.
On Niagara we can get unimplemented fpop, so handle that.
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Sun, 19 Feb 2006 00:36:39 +0000 (16:36 -0800)]
[SPARC64]: Set %gl to 1 in kvmap_itlb_longpath on SUN4V.
Just like kvmap_dtlb_longpath we have to force the
global register level to one in order to mimick the
PSTATE_MG --> PSTATE_AG trasition done on SUN4U.
Signed-off-by: David S. Miller <davem@davemloft.net>
projects / linux-2.6 / log