Jan Beulich [Mon, 12 Sep 2005 16:49:24 +0000 (18:49 +0200)]
[PATCH] x86-64: Fix CFI information
Being the foundation for reliable stack unwinding, this fixes CFI unwind
annotations in many low-level x86_64 routines, plus a config option
(available to all architectures, and also present in the previously sent
patch adding such annotations to i386 code) to enable them separatly
rather than only along with adding full debug information.
[PATCH] x86-64: Remove freeing of SMP trampoline pages
Nick points out it never worked because PageReserved was
set and it might cause problems later on. Also HOTPLUG_CPU
is much more common now so let's care not too much
about the !hotplug case.
Needed for some newer Opteron systems with E stepping and memory
relocation enabled. The node addresses are different in lower
bits now so the nodemap hash function needs to be enlarged.
If one of the arguments (in the _llseek syscall it's the arg4) is a pointer
which the syscall is expected to write to (to the memory pointed to by this
ptr), then this side-effect is not captured in the asm.
If anyone uses this macro to define it's own version of the syscall
(sometimes necessary when not using glibc) and it's inlined, then GCC
doesn't know that this asm write to "*dest", when called like so for instance:
out = 1;
llseek (fd, bla, blubb, &out, trara)
use (out);
Here nobody tells GCC that "out" actually is written to (just a pointer to it
is passed to the asm). Hence GCC might (and in the above bug did)
copy-propagate "1" into the second use of "out".
The easiest solution would be to add a "memory" clobber to the definition
of this syscall macro. As this is a syscall, it shouldn't inhibit too many
optimizations.
The generic TLB flush functions kept upto 506 pages per
CPU to avoid too frequent IPIs.
This value was done for the L1 cache of older x86 CPUs,
but with modern CPUs it does not make much sense anymore.
TLB flushing is slow enough that using the L2 cache is fine.
This patch increases the flush array on x86-64 to cache
5350 pages. That is roughly 20MB with 4K pages. It speeds
up large munmaps in multithreaded processes on SMP considerably.
The cost is roughly 42k of memory per CPU, which is reasonable.
I only increased it on x86-64 for now, but it would probably
make sense to increase it everywhere. Embedded architectures
with SMP may keep it smaller to save some memory per CPU.
[PATCH] x86-64: Make remote TLB flush more scalable
Instead of using a global spinlock to protect the state
of the remote TLB flush use a lock and state for each sending CPU.
To tell the receiver where to look for the state use 8 different
call vectors. Each CPU uses a specific vector to trigger flushes on other
CPUs. Depending on the received vector the target CPUs look into
the right per cpu variable for the flush data.
When the system has more than 8 CPUs they are hashed to the 8 available
vectors. The limited global vector space forces us to this right now.
In future when interrupts are split into per CPU domains this could be
fixed, at the cost of needing more IPIs in flat mode.
Also some minor cleanup in the smp flush code and remove some outdated
debug code.
Requires patch to move cpu_possible_map setup earlier.
If we use 64bit kernel on ia64/x86_64/s390 architecture, and we run
32bit binary on 32bit compatibility mode, sendfile system call seems be
not set offset argument.
This is because sendfile's return value is not zero but the code regards
the result by return value is zero or not.
This problem will be affect to ia64/x86_64/s390 and not affect to other
architecture does not affect other architecture (mips/parisc/ppc64/sparc64).
[PATCH] x86-64: Make lockless machine check record passing a bit more robust.
One machine is constantly throwing NMI watchdog timeouts in mce_log
This was one attempt to fix it.
(AK: this doesn't actually fix the bug I'm seeing unfortunately, probably
drop. I don't like it that the reader can spin forever now waiting
for a writer)
This leads to bootmem allocating first from node 0 instead
of from the last node. This avoids swiotlb allocating on the last node, which
doesn't really work on a machine with >4GB.
Note: there is a better patch around from someone else that gets
rid of the pgdat list completely.
[PATCH] x86-64: Avoid unnecessary double bouncing for swiotlb
PCI_DMA_BUS_IS_PHYS has to be zero even when the GART IOMMU is disabled
and the swiotlb is used. Otherwise the block layer does unnecessary
double bouncing.
[PATCH] x86-64: Support dualcore and 8 socket systems in k8 fallback node parsing
In particular on systems where the local APIC space and node space
is very different from the Linux CPU number space.
Previously the older NUMA setup code directly parsing the K8
northbridge registers had some issues on 8 socket or dual core
systems. This patch fixes them.
This is mainly done by fixing some confusion between Linux
CPU numbers and local APIC ids. We now pass the local APIC IDs
to later code, which avoids mismatches.
Also add some heuristics to detect cases where the Hypertransport
nodeids and the local APIC IDs don't match, but are shifted
by a constant offset.
This is still all quite hackish, hopefully BIOS writers fill
in correct SRATs instead.
[PATCH] x86-64: Don't assign CPU numbers in SRAT parsing
Do that later when the CPU boots. SRAT just stores the APIC<->Node
mapping node. This fixes problems on systems where the order
of SRAT entries does not match the MADT.
Paul Jackson [Mon, 12 Sep 2005 11:30:30 +0000 (04:30 -0700)]
[PATCH] cpuset semaphore depth check optimize
Optimize the deadlock avoidance check on the global cpuset
semaphore cpuset_sem. Instead of adding a depth counter to the
task struct of each task, rather just two words are enough, one
to store the depth and the other the current cpuset_sem holder.
Thanks to Nikita Danilov for the idea.
Signed-off-by: Paul Jackson <pj@sgi.com>
[ We may want to change this further, but at least it's now
a totally internal decision to the cpusets code ]
Mark ia64-specific MCA/INIT scheduler hooks as dangerous
..and only enable them for ia64. The functions are only valid
when the whole system has been totally stopped and no scheduler
activity is ongoing on any CPU, and interrupts are globally
disabled.
In other words, they aren't useful for anything else. So make
sure that nobody can use them by mistake.
Anton Blanchard [Sat, 10 Sep 2005 06:01:10 +0000 (16:01 +1000)]
[PATCH] ppc64: Add definitions for new PTRACE calls
- Add PTRACE_GET_DEBUGREG/PTRACE_SET_DEBUGREG. The definition is
as follows:
/*
* Get or set a debug register. The first 16 are DABR registers and the
* second 16 are IABR registers.
*/
#define PTRACE_GET_DEBUGREG 25
#define PTRACE_SET_DEBUGREG 26
DABR == data breakpoint and IABR = instruction breakpoint in IBM
speak. We could split out the IABR into 2 more ptrace calls but I
figured there was no need and 16 DABR registers should be more
than enough (POWER4/POWER5 have one).
- Add 2 new SIGTRAP si_codes: TRAP_HWBKPT and TRAP_BRANCH. I couldnt
find any standards on either of these so I copied what ia64 is
doing. Again this might be better placed in
include/asm-generic/siginfo.h
Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Anton Blanchard [Sat, 10 Sep 2005 06:01:08 +0000 (16:01 +1000)]
[PATCH] ppc64: ptrace cleanups
- Remove the PPC_REG* defines
- Wrap some more stuff with ifdef __KERNEL__
- Add missing PT_TRAP, PT_DAR, PT_DSISR defines
- Add PTRACE_GETEVRREGS/PTRACE_SETEVRREGS, even though we dont use it on
ppc64 we dont want to allocate them for something else.
Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Robert Jennings [Sat, 10 Sep 2005 06:01:07 +0000 (16:01 +1000)]
[PATCH] ppc64: Add PTRACE_{GET|SET}VRREGS
The ptrace get and set methods for VMX/Altivec registers present in the
ppc tree were missing for ppc64. This patch adds the 32-bit and
64-bit methods. Updated with the suggestions from Anton following the lines
of his code snippet.
Added:
- flush_altivec_to_thread calls as suggested by Anton
- piecewise copy of structure to preserve 32-bit vrsave data as per
Anton
(I consolidated the 32 and 64bit versions with 2 helper macros - Anton)
Signed-off-by: Robert C Jennings <rcjenn@austin.ibm.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Paul Mackerras [Mon, 12 Sep 2005 07:17:36 +0000 (17:17 +1000)]
ppc64: Set up PCI tree from Open Firmware device tree
This adds code which gives us the option on ppc64 of instantiating the
PCI tree (the tree of pci_bus and pci_dev structs) from the Open
Firmware device tree rather than by probing PCI configuration space.
The OF device tree has a node for each PCI device and bridge in the
system, with properties that tell us what addresses the firmware has
configured for them and other details.
There are a couple of reasons why this is needed. First, on systems
with a hypervisor, there is a PCI-PCI bridge per slot under the PCI
host bridges. These PCI-PCI bridges have special isolation features
for virtualization. We can't write to their config space, and we are
not supposed to be reading their config space either. The firmware
tells us about the address ranges that they pass in the OF device
tree.
Secondly, on powermacs, the interrupt controller is in a PCI device
that may be behind a PCI-PCI bridge. If we happened to take an
interrupt just at the point when the device or a bridge on the path to
it was disabled for probing, we would crash when we try to access the
interrupt controller.
I have implemented a platform-specific function which is called for
each PCI bridge (host or PCI-PCI) to say whether the code should look
in the device tree or use normal PCI probing for the devices under
that bridge. On pSeries machines we use the device tree if we're
running under a hypervisor, otherwise we use normal probing. On
powermacs we use normal probing for the AGP bridge, since the device
for the AGP bridge itself isn't shown in the device tree (at least on
my G5), and the device tree for everything else.
This has been tested on a dual G5 powermac, a partition on a POWER5
machine (running under the hypervisor), and a legacy iSeries
partition.
[PATCH] i810fb: Change option ext_vga to extvga to match documentation
Reported by: Manuel Lauss <mano@roarinelk.homelinux.net>
He was getting random initial video modes depending on the kernel
configuration. His option line includes 'extvga'.
The i810fb documentation describes the option 'extvga', however the
driver accepts 'ext_vga'. Besides 'extvga' being ignored by i810fb,
it also confuses the option parser of i810fb and assigns 'extvga' to
'mode_option'. This leads to an incorrect video mode at boot time.
[PATCH] m68knommu: common RAM based 68360 startup code
Create common start code for all 68360 based platforms that are
loaded and run directly from RAM (as opposed to running from
flash/ROM). This replaces the old specific startup code for
each board.
[PATCH] m68knommu: allow for SDRAM and GPIO differences on 5270/1 and 5274/5 processors
Allow for differences in the SDRAM controller setup and GPIO pin setup
of the 5270/1 and 5274/5 parts. With separate config options for each
now this no longer needs to be board specific.
[PATCH] uclinux: add NULL check, 0 end valid check and some more exports to nommu.c
Move call to get_mm_counter() in update_mem_hiwater() to be
inside the check for tsk->mm being null. Otherwise you can be
following a null pointer here. This patch submitted by
Javier Herrero <jherrero@hvsistemas.es>.
Modify the end check for munmap regions to allow for the
legacy behavior of 0 being valid. Pretty much all current
uClinux system libc malloc's pass in 0 as the end point.
A hard check will fail on these, so change the check so
that if it is non-zero it must be valid otherwise it fails.
A passed in value will always succeed (as it used too).
Also export a few more mm system functions - to be consistent
with the VM code exports.
[PATCH] uclinux: remove use of mtd_put_device() in uclinux MTD map driver
We should not call mtd_put_device() in the uclinux MTD map driver.
Also consistently use phys/virt fields of maps map_info struct,
instead of mixing it with map_priv_1.
[PATCH] m68knommu: common ROM/flash based 68360 startup code
Create common start code for all 68360 based platforms that are
loaded and run directly from ROM/flash (as opposed to running from
RAM). This replaces the old specific startup code for each board.
[PATCH] m68knommu: cache support for 523x/528x processors
Add support for the cache of the ColdFIre 523x family of processors.
Enable the 528x cache by default now, all final shipping silicon
has the cache bug fixed.
[PATCH] m68knommu: ColdFire FEC eth driver improvements
A few improvements to the Freescale/ColdFire FEC driver:
. some formatting cleanups
. add support for the FEC device in the ColdFire 523x processor family
. add support for MAC address setting on MOD5272 and M5272C3 boards
. don't re-read the PHY status register many times
. ack status interrupt before reading status register
. move printing init message to after full init (so that the
ethX name is filled out for printing)
Some parts of this patch submitted by Philippe De Muyter <phdm@macqel.be>
[PATCH] m68knommu: config support for FEC eth of 523x Coldfire processor family
Add configuration support for the FEC ethernet controller in the
Freescale 523x processor family. Also add and option to configure
the second FEC controller on some Freescale processors.
projects / linux-2.6 / log