Matthew Wilcox [Thu, 16 Nov 2006 20:40:53 +0000 (13:40 -0700)]
[IA64] Fix DISCONTIGMEM without VIRTUAL_MEM_MAP
make allnoconfig currently fails to build because it selects DISCONTIGMEM
without VIRTUAL_MEM_MAP. I see no particular reason this combination
ought to fail, so I fixed it by:
- Including memory_model.h in all circumstances, except when both
DISCONTIGMEM and VIRTUAL_MEM_MAP are enabled.
- Defining ia64_pfn_valid() to 1 unless VIRTUAL_MEM_MAP is enabled
Signed-off-by: Matthew Wilcox <matthew@wil.cx> Signed-off-by: Tony Luck <tony.luck@intel.com>
[PATCH] Add support for type argument in PAL_GET_PSTATE
PAL_GET_PSTATE accepts a type argument to return different kinds of
frequency information.
Refer: Intel Itanium®Architecture Software Developer's Manual -
Volume 2: System Architecture, Revision 2.2
(http://developer.intel.com/design/itanium/manuals/245318.htm)
Add the support for type argument and use Instantaneous frequency
in the acpi driver.
Also fix a bug, where in return value of PAL_GET_PSTATE was getting compared
with 'control' bits instead of 'status' bits.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Chen, Kenneth W [Thu, 9 Nov 2006 00:29:25 +0000 (16:29 -0800)]
[IA64] tidy up return value of ip_fast_csum
While working on implementing csum_ipv6_magic, I noticed that current
version of ip_fast_csum will potentially return bits above "unsigned
short" as 1. While no harm is done right now because all call sites
will chop off the upper bits when it uses the return value. However,
this is still dangerous and buggy. Here is a patch to enforce that the
function really returns unsigned short in the native register format.
The fix is free as there are plenty open slot to add one more asm instruction.
Signed-off-by: Ken Chen <kenneth.w.chen@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Russ Anderson [Thu, 7 Dec 2006 19:06:35 +0000 (11:06 -0800)]
[IA64] Update processor_info features
Add the printing of additional processor features to proc_features.
Based on Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software
Developer's Manual" (January 2006) fields (pages 2:430-2:432).
This patch gets the features back in sync with the spec.
Sample output before:
--------------------------------------------------------------
cobra:~ # cat /proc/pal/cpu0/processor_info
XIP,XPSR,XFS implemented : On NoCtrl
XR1-XR3 implemented : On NoCtrl
Disable dynamic predicate prediction : NotImpl
Disable processor physical number : NotImpl
Disable dynamic data cache prefetch : NotImpl
Disable dynamic inst cache prefetch : NotImpl
Disable dynamic branch prediction : NotImpl
Disable BINIT on processor time-out : On Ctrl
Disable dynamic power management (DPM) : NotImpl
Disable coherency : NotImpl
Disable cache : NotImpl
Enable CMCI promotion : Off Ctrl
Enable MCA to BINIT promotion : Off Ctrl
Enable MCA promotion : NotImpl
Enable BERR promotion : NotImpl
cobra:~ #
--------------------------------------------------------------
Sample output after:
--------------------------------------------------------------
cobra:~ # cat /proc/pal/cpu0/processor_info
Unimplemented instruction address fault : NotImpl
INIT, PMI, and LINT pins : NotImpl
Simple unimplimented instr addresses : On NoCtrl
Variable P-state performance : NotImpl
Virtual machine features implemeted : On NoCtrl
XIP,XPSR,XFS implemented : On NoCtrl
XR1-XR3 implemented : On NoCtrl
Disable dynamic predicate prediction : NotImpl
Disable processor physical number : NotImpl
Disable dynamic data cache prefetch : NotImpl
Disable dynamic inst cache prefetch : NotImpl
Disable dynamic branch prediction : NotImpl
Disable P-states : Off Ctrl
Enable MCA on Data Poisoning : Off Ctrl
Enable vmsw instruction : On Ctrl
Enable extern environmental notification : NotImpl
Disable BINIT on processor time-out : On Ctrl
Disable dynamic power management (DPM) : NotImpl
Disable coherency : NotImpl
Disable cache : NotImpl
Enable CMCI promotion : Off Ctrl
Enable MCA to BINIT promotion : Off Ctrl
Enable MCA promotion : NotImpl
Enable BERR promotion : NotImpl
cobra:~ #
--------------------------------------------------------------
Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck <tony.luck@intel.com>
Russ Anderson [Thu, 26 Oct 2006 16:53:17 +0000 (11:53 -0500)]
[IA64] Add se bit to Processor State Parameter structure
Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's
Manual" (January 2006) adds a se bit to the Processor State Parameter
fields (pages 2:299). This patch gets the structs back in sync
with the spec.
Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck <tony.luck@intel.com>
Russ Anderson [Wed, 25 Oct 2006 19:18:27 +0000 (14:18 -0500)]
[IA64] Add dp bit to cache and bus check structs
Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's
Manual" (January 2006) adds a dp bit to the cache_check and bus_check
fields (pages 2:401-2:404). This patch gets the structs back in sync
with the spec.
Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck <tony.luck@intel.com>
John Keller [Mon, 6 Nov 2006 20:10:50 +0000 (14:10 -0600)]
[IA64] SN: Correctly update smp_affinty mask
On Altix systems, the /proc/irq/nn/smp_affinity mask is not being setup
at device iniitalization, or updated after an interrupt redirection.
This patch resolves those issues.
Signed-off-by: John Keller <jpk@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Zou Nan hai [Thu, 7 Dec 2006 17:51:35 +0000 (09:51 -0800)]
[IA64] IA64 Kexec/kdump
Changes and updates.
1. Remove fake rendz path and related code according to discuss with Khalid Aziz.
2. fc.i offset fix in relocate_kernel.S.
3. iospic shutdown code eoi and mask race fix from Fujitsu.
4. Warm boot hook in machine_kexec to SN SAL code from Jack Steiner.
5. Send slave to SAL slave loop patch from Jay Lan.
6. Kdump on non-recoverable MCA event patch from Jay Lan
7. Use CTL_UNNUMBERED in kdump_on_init sysctl.
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Jesper Juhl [Wed, 6 Dec 2006 23:45:58 +0000 (00:45 +0100)]
[PATCH] A few small additions and corrections to README
Here's a small patch which
- adds a few archs to the current list of supported platforms.
- adds a few missing slashes at the end of URLs.
- adds a few references to additional documentation.
- adds "make config" to the list of possible configuration targets.
- makes a few other minor changes.
Signed-off-by: Jesper Juhl <jesper.juhl@gmail.com>
[ Ben Nizette <ben.nizette@iinet.net.au> points out AVR32 arch too ] Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Jesper Juhl [Wed, 6 Dec 2006 23:16:26 +0000 (00:16 +0100)]
[PATCH] Clean up 'make help' output for documentation targets.
Here's a patch that cleans up the "make help" output a bit for the
documentation targets.
Currently the documentation targets are listed completely different than
all the other targets :
Documentation targets:
Linux kernel internal documentation in different formats:
xmldocs (XML DocBook), psdocs (Postscript), pdfdocs (PDF)
htmldocs (HTML), mandocs (man pages, use installmandocs to install)
with this patch they are more in line with the rest of the output :
Documentation targets:
Linux kernel internal documentation in different formats:
htmldocs - HTML
installmandocs - install man pages generated by mandocs
mandocs - man pages
pdfdocs - PDF
psdocs - Postscript
xmldocs - XML DocBook
Linus Torvalds [Thu, 7 Dec 2006 00:17:37 +0000 (16:17 -0800)]
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Import updates from i386's i8259.c
[MIPS] *-berr: Header inclusions for DEC bus error handlers
[MIPS] Compile __do_IRQ() when really needed
[MIPS] genirq: use name instead of typename
[MIPS] Do not use handle_level_irq for ioasic_dma_irq_type.
[MIPS] pte_offset(dir,addr): parenthesis fix
Linus Torvalds [Wed, 6 Dec 2006 22:42:57 +0000 (14:42 -0800)]
x86[-64]:Remove 'volatile' from atomic_t
Any code that relies on the volatile would be a bug waiting to happen
anyway.
Don't encourage people to think that putting 'volatile' on data
structures somehow fixes problems. We should always use proper locking
(and other serialization) techniques.
Franck Bui-Huu [Fri, 1 Dec 2006 17:22:27 +0000 (18:22 +0100)]
[MIPS] Compile __do_IRQ() when really needed
__do_IRQ() is needed only by irq handlers that can't use
default handlers defined in kernel/irq/chip.c.
For others platforms there's no need to compile this function
since it won't be used. For those platforms this patch defines
GENERIC_HARDIRQS_NO__DO_IRQ symbol which is used exactly for
this purpose.
Futhermore for platforms which do not use __do_IRQ(), end()
method which is part of the 'irq_chip' structure is not used.
This patch simply removes this method in this case.
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (43 commits)
sh: sh775x/titan fixes for irq header changes.
sh: update r7780rp defconfig.
sh: compile fixes for header cleanup.
sh: Fixup pte_mkhuge() build failure.
sh: set KBUILD_IMAGE to something sensible.
sh: show held locks in stack trace with lockdep.
sh: platform_pata support for R7780RP
sh: stacktrace/lockdep/irqflags tracing support.
sh: Fixup movli.l/movco.l atomic ops for gcc4.
sh: dyntick infrastructure.
sh: Clock framework tidying.
sh: Turn off IRQs around get_timer_offset() calls.
sh: Get the PGD right in oops case with 64-bit PTEs.
sh: Fix store queue bitmap end.
sh: More flexible + SH7780 earlyprintk SCIF support.
sh: Fixup various PAGE_SIZE == 4096 assumptions.
sh: Fixup 4K irq stacks.
sh: dma-api channel capability extensions.
sh: Drop name overload in dma-sh.
sh: Make dma-isa depend on ISA_DMA_API.
...
* git://git.infradead.org/users/dhowells/workq-2.6:
Actually update the fixed up compile failures.
WorkQueue: Fix up arch-specific work items where possible
WorkStruct: make allyesconfig
WorkStruct: Pass the work_struct pointer instead of context data
WorkStruct: Merge the pending bit into the wq_data pointer
WorkStruct: Typedef the work function prototype
WorkStruct: Separate delayable and non-delayable events.
Mike Frysinger [Wed, 6 Dec 2006 02:02:59 +0000 (12:02 +1000)]
[PATCH] uclinux: fix mmap() of directory for nommu case
I was playing with blackfin when i hit a neat bug ... doing an open() on a
directory and then passing that fd to mmap() would cause the kernel to hang
after poking into the code a bit more, i found that
mm/nommu.c:validate_mmap_request() checks the length and if it is 0, just
returns the address ... this is in stark contrast to mmu's
mm/mmap.c:do_mmap_pgoff() where it returns -EINVAL for 0 length requests ...
i then noticed that some other parts of the logic is out of date between the
two funcs, so perhaps that's the easy fix ?
Gavin Lambert [Wed, 6 Dec 2006 01:57:53 +0000 (11:57 +1000)]
[PATCH] m68knommu: remove FP conditionals in ucontext struct
The first patch is to the 2.6 kernel include file (for m68knommu), to get
rid of the conditional definitions, otherwise the structures have different
sizes depending on whether there's an FPU or not.
Greg Ungerer [Wed, 6 Dec 2006 01:49:34 +0000 (11:49 +1000)]
[PATCH] m68knommu: ColdFire serial driver fixes
Some updates for the old ColdFire serial driver:
. support 3 and 4 UARTs on some ColdFire parts that have them
. enable multifunction pins to serial for 527x CPU's
. support the 5272 UART's fractional baud rate divisor
. switch driver name to "mcfserial"
Greg Ungerer [Wed, 6 Dec 2006 01:36:59 +0000 (11:36 +1000)]
[PATCH] m68knommu: fix timer register access on 523x ColdFire platforms
The 523x timer TRR register is a full 32bits, the older register (on
other ColdFire parts) was only 16 bits. Use the right type of
__raw_read when accessing it.
Problem found by Yaroslav Vinogradov <yaroslav.vinogradov@freescale.com>
Jamie Lenehan [Wed, 6 Dec 2006 03:05:02 +0000 (12:05 +0900)]
sh: sh775x/titan fixes for irq header changes.
The following moves the creation of IPR interupts into setup-7750.c
and updates a few other things to make it all work after the "Drop
CPU subtype IRQ headers" commit. It boots and runs fine on my titan
board.
- adds an ipr_idx to the ipr_data and uses a function in the subtype
code to calculate the address of the IPR registers
- adds a function to enable individual interrupt mode for externals
in the subtype code and calls that from the titan board code
instead of doing it directly.
- I changed the shift in the ipr_data to be the actual # of bits to
shift, instead of the numnber / 4 - made it easier to match with
the manual.
Signed-off-by: Jamie Lenehan <lenehan@twibble.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Paul Mundt [Wed, 6 Dec 2006 02:20:53 +0000 (11:20 +0900)]
sh: Fixup pte_mkhuge() build failure.
When hugetlbpage support isn't enabled, this can be bogus.
Wrap it back in _PAGE_FLAGS_HARD to avoid changes to the
base PTE when not aiming for larger sizes.
Paul Mundt [Fri, 1 Dec 2006 05:32:54 +0000 (14:32 +0900)]
sh: Fixup movli.l/movco.l atomic ops for gcc4.
gcc4 gets a bit pissy about the outputs:
include/asm/atomic.h: In function 'atomic_add':
include/asm/atomic.h:37: error: invalid lvalue in asm statement
include/asm/atomic.h:30: error: invalid lvalue in asm output 1
...
this ended up being a thinko anyways, so just fix it up.
Verified for proper behaviour with the older toolchains, too.
Paul Mundt [Fri, 1 Dec 2006 04:23:47 +0000 (13:23 +0900)]
sh: dyntick infrastructure.
This adds basic NO_IDLE_HZ support to the SH timer API so timers
are able to wire it up. Taken from the ARM version, as it fit in
to our API with very few changes needed.
Paul Mundt [Fri, 1 Dec 2006 04:15:14 +0000 (13:15 +0900)]
sh: Clock framework tidying.
This syncs up the SH clock framework with the linux/clk.h API,
for which there were only some minor changes required, namely
the clk_get() dev_id and subsequent callsites.
Paul Mundt [Fri, 1 Dec 2006 04:12:05 +0000 (13:12 +0900)]
sh: Turn off IRQs around get_timer_offset() calls.
Since all of the sys_timer sources currently do this on their own
within the ->get_offset() path, it's more sensible to just have
the caller take care of it when grabbing xtime_lock. Incidentally,
this is more in line with what others (ie, ARM) are doing already.
Paul Mundt [Fri, 1 Dec 2006 03:14:11 +0000 (12:14 +0900)]
sh: Get the PGD right in oops case with 64-bit PTEs.
Previously this was using a static pgd shift in the reporting
code, simply flip this to PGDIR_SHIFT which does the right
thing depending on varying PTE magnitudes on the SH-X2 MMU.
While we're at it, and since it's been recently added, use
get_TTB() for fetching the TTB, rather than the open coded
instructions.
Paul Mundt [Fri, 1 Dec 2006 03:01:43 +0000 (12:01 +0900)]
sh: Fix store queue bitmap end.
The end of the store queue bitmap is miscalculated when searching
for a free range in sq_remap(), missing the PAGE_SHIFT shift that's
done in sq_api_init(). This runs in to workloads where we can scan
beyond the end of the bitmap.
Paul Mundt [Mon, 27 Nov 2006 03:10:23 +0000 (12:10 +0900)]
sh: More flexible + SH7780 earlyprintk SCIF support.
This makes the early printk support somewhat more flexible,
moving the port definition to a config option, and making the
port initialization configurable for sh-ipl+g users.
At the same time, this allows us to trivially wire up the
SH7780 SCIF0, so that's thrown in too more or less for free.
Paul Mundt [Mon, 27 Nov 2006 03:06:26 +0000 (12:06 +0900)]
sh: Fixup various PAGE_SIZE == 4096 assumptions.
There were a number of places that made evil PAGE_SIZE == 4k
assumptions that ended up breaking when trying to play with
8k and 64k page sizes, this fixes those up.
The most significant change is the way we load THREAD_SIZE,
previously this was done via:
mov #(THREAD_SIZE >> 8), reg
shll8 reg
to avoid a memory access and allow the immediate load. With
a 64k PAGE_SIZE, we're out of range for the immediate load
size without resorting to special instructions available in
later ISAs (movi20s and so on). The "workaround" for this is
to bump up the shift to 10 and insert a shll2, which gives a
bit more flexibility while still being much cheaper than a
memory access.
Paul Mundt [Fri, 24 Nov 2006 10:46:18 +0000 (19:46 +0900)]
sh: Fixup 4K irq stacks.
There was a clobber issue with the register we were saving
the stack in, so we switch to a register that we handle in
the clobber list properly already.
This also follows the x86 changes for allowing the softirq
checks from hardirq context.
Mark Glaisher [Fri, 24 Nov 2006 06:13:52 +0000 (15:13 +0900)]
sh: dma-api channel capability extensions.
This extends the SH DMA API for allowing handling of DMA
channels based off of their respective capabilities.
A couple of functions are added to the existing API,
the core bits are register_chan_caps() for registering
channel capabilities, and request_dma_bycap() for fetching
a channel dynamically based off of a capability set.
Signed-off-by: Mark Glaisher <mark.glaisher@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Paul Mundt [Fri, 24 Nov 2006 05:50:05 +0000 (14:50 +0900)]
sh: Drop name overload in dma-sh.
Pass along the dev_id from request_dma() all the way down,
rather than inserting an artificial name relating to the TEI
line that we were doing before.
This makes the line a bit less obvious, but dev_id is the proper
behaviour for this regardless.
Stuart Menefy [Fri, 24 Nov 2006 04:01:36 +0000 (13:01 +0900)]
sh: Fix syscall tracing ordering.
The implementation of system call tracing in the kernel has a
couple of ordering problems:
- the validity of the system call number is checked before
calling out to system call tracing code, and should be
done after
- the system call number used when tracing is the one the
system call was invoked with, while the system call tracing
code can legitimatly change the call number (for example
strace permutes fork into clone)
This patch fixes both of these problems, and also reoders the
code slightly to make the direct path through the code the
common case.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Paul Mundt [Fri, 24 Nov 2006 02:22:57 +0000 (11:22 +0900)]
sh: generic push-switch framework.
This adds support for a generic push switch framework. Adaptable for
various switches, including GPIO switches and the push switches commonly
found on Renesas debug boards.
This allows switch states to be trivially reported through sysfs.
Stuart Menefy [Tue, 21 Nov 2006 06:38:05 +0000 (15:38 +0900)]
sh: pmd rework.
Remove extra bits from the pmd structure and store a kernel logical
address rather than a physical address. This allows it to be directly
dereferenced. Another piece of wierdness inherited from x86.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Stuart Menefy [Tue, 21 Nov 2006 02:16:57 +0000 (11:16 +0900)]
sh: gcc4 support.
This fixes up the kernel for gcc4. The existing exception handlers
needed some wrapping for pt_regs access, acessing the registers
via a RELOC_HIDE() pointer.
The strcpy() issues popped up here too, so add -ffreestanding and
kill off the symbol export.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Paul Mundt [Tue, 21 Nov 2006 02:12:19 +0000 (11:12 +0900)]
sh: Explicit endian selection support.
Previously big endian was simply assumed if little endian was
not set, which led to some cflags ordering issues. There's not
much point to not having a big endian option, so shove one in
a choice and wire it up in the Makefile.
This lets us clean up some of the cflags ordering while we're
at it.
Paul Mundt [Mon, 20 Nov 2006 05:30:26 +0000 (14:30 +0900)]
sh: Preliminary support for SH-X2 MMU.
This adds some preliminary support for the SH-X2 MMU, used by
newer SH-4A parts (particularly SH7785).
This MMU implements a 'compat' mode with SH-X MMUs and an
'extended' mode for SH-X2 extended features. Extended features
include additional page sizes (8kB, 4MB, 64MB), as well as the
addition of page execute permissions.
The extended mode attributes are placed in a second data array,
which requires us to switch to 64-bit PTEs when in X2 mode.
With the addition of the exec perms, we also overhaul the mmap
prots somewhat, now that it's possible to handle them more
intelligently.
Paul Mundt [Mon, 20 Nov 2006 04:55:34 +0000 (13:55 +0900)]
sh: Drop CPU subtype IRQ headers.
This drops the various IRQ headers that were floating around
and primarily providing hardcoded IRQ definitions for the
various CPU subtypes. This quickly got to be an unmaintainable
mess, made even more evident by the subtle breakage introduced
by the SH-2 and SH-2A changes.
Now that subtypes are able to register IRQ maps directly, just
rip all of the headers out.
Ed Lin [Tue, 5 Dec 2006 01:49:42 +0000 (17:49 -0800)]
[SCSI] stex: change wait loop code
The original wait loop may be much longer than intended time.
Use more accurate timer_after for it. Also adjust wait value to
avoid unnecessary long waiting.
Signed-off-by: Ed Lin <ed.lin@promise.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Ed Lin [Tue, 5 Dec 2006 01:49:36 +0000 (17:49 -0800)]
[SCSI] stex: update device id info
- add comments for various devices
- remove unused device ids(0xf350, 0x4301, 0x8301, 0x8302)
- add new device id(0xe350)
- fix vendor id of st_vsc
- modify Kconfig help info
Signed-off-by: Ed Lin <ed.lin@promise.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Jeff Garzik [Mon, 4 Dec 2006 01:49:23 +0000 (20:49 -0500)]
[SCSI] megaraid: fix MMIO casts
megaraid's MMIO RD*/WR* macros directly call readl() and writel() with
an 'unsigned long' argument. This throws a warning, but is otherwise OK
because the 'unsigned long' is really the result of ioremap(). This
setup is also OK because the variable can hold an ioremap cookie /or/ a
PCI I/O port (PIO).
However, to fix the warning thrown when readl() and writel() are passed
an unsigned long cookie, I introduce 'void __iomem *mmio_base', holding
the same value as 'base'. This will silence the warnings, and also
cause an oops whenever these MMIO-only functions are ever accidentally
passed an I/O address.
Signed-off-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
projects / linux-2.6 / log