Keith Owens [Mon, 26 Jun 2006 11:59:41 +0000 (13:59 +0200)]
[PATCH] x86_64: Standardize i386/x86_64 handling of NMI_VECTOR
x86_64 and i386 behave inconsistently when sending an IPI on vector 2
(NMI_VECTOR). Make both behave the same, so IPI 2 is sent as NMI.
The crash code was abusing send_IPI_allbutself() by passing a code
instead of a vector, it only worked because crash knew about the
internal code of send_IPI_allbutself(). Change crash to use NMI_VECTOR
instead, and remove the comment about how crash was abusing the function.
This patch is a pre-requisite for fixing the problem where sending an
IPI as NMI would reboot some Dell Xeon systems. I cannot fix that
problem while crash continus to abuse send_IPI_allbutself().
It also removes the inconsistency between i386 and x86_64 for
NMI_VECTOR. That will simplify all the RAS code that needs to bring
all the cpus to a clean stop, even when one or more cpus are spinning
disabled.
Sergey Vlasov [Mon, 26 Jun 2006 11:59:32 +0000 (13:59 +0200)]
[PATCH] x86_64: Do not use -ffunction-sections for modules
Currently CONFIG_REORDER uses -ffunction-sections for all code;
however, creating a separate section for each function is not useful
for modules and just adds bloat. Moving this option from CFLAGS to
CFLAGS_KERNEL shrinks module object files (e.g., the module tree for a
kernel built with most drivers as modules shrinked from 54M to 46M),
and decreases the number of sysfs files in /sys/module/*/sections/
directories.
Defaulting to a value not evenly divisible by four makes little sense,
as four values are displayed per line (and hence the rest of the line
would otherwise be wasted).
Rohit Seth [Mon, 26 Jun 2006 11:59:14 +0000 (13:59 +0200)]
[PATCH] x86_64: x86_64 setup.c - printing cmp related boottime information
Getting phys_proc_id and cpu_core_id information to be printed at boot
time for AMD processors. Also matching the Node related boot time
information that gets printed for Intel and AMD processors for NUMA
configurations.
Andi Kleen [Mon, 26 Jun 2006 11:59:11 +0000 (13:59 +0200)]
[PATCH] i386/x86-64/ia64: Move polling flag into thread_info_status
During some profiling I noticed that default_idle causes a lot of
memory traffic. I think that is caused by the atomic operations
to clear/set the polling flag in thread_info. There is actually
no reason to make this atomic - only the idle thread does it
to itself, other CPUs only read it. So I moved it into ti->status.
Converted i386/x86-64/ia64 for now because that was the easiest
way to fix ACPI which also manipulates these flags in its idle
function.
Cc: Nick Piggin <npiggin@novell.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Len Brown <len.brown@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Jan Beulich [Mon, 26 Jun 2006 11:59:02 +0000 (13:59 +0200)]
[PATCH] x86_64: miscellaneous mm/init.c fixes
- fix an off-by-one error in phys_pmd_init()
- prevent phys_pmd_init() from removing mappings established earlier
- fix the direct mapping early printk to in fact show the end of the range
- remove an apparently orphan comment
Jacob Shin [Mon, 26 Jun 2006 11:58:50 +0000 (13:58 +0200)]
[PATCH] x86_64: mce_amd relocate sysfs files
Get rid of /sys/devices/system/threshold directory and move
mce_amd thresholding files into the machine sysfs directory --
/sys/devices/system/machinecheck.
Vojtech Pavlik [Mon, 26 Jun 2006 11:58:35 +0000 (13:58 +0200)]
[PATCH] x86_64: Explain why HPET T0_CMP register is written twice
After writing the CFG register, the first value written to the T0_CMP
register is the value at which next interrupt should be triggered, every
value after that sets the period of the interrupt. For that reason, the code
needs to write the value twice - to set both the phase and period.
[AK: I had already figured it out by myself, but it's still useful
to have a comment for this.]
Vojtech Pavlik [Mon, 26 Jun 2006 11:58:26 +0000 (13:58 +0200)]
[PATCH] x86_64: Add X86_FEATURE_RDTSCP, fix rdtscp in /proc/cpuinfo
This patch adds the X86_FEATURE_RDTSCP #define, so that kernel code can
check for the feature easily and also fixes the location of the "rdtscp"
string in the cpuinfo tables.
Vojtech Pavlik [Mon, 26 Jun 2006 11:58:20 +0000 (13:58 +0200)]
[PATCH] x86_64: Add useful constants to time.h
In timekeeping code, one often does need to use conversion constants. Naming
these leads to code that's easier to understand, showing the reader between
which units the conversion is made.
Rohit Seth [Mon, 26 Jun 2006 11:58:17 +0000 (13:58 +0200)]
[PATCH] x86_64: moving phys_proc_id and cpu_core_id to cpuinfo_x86
Most of the fields of cpuinfo are defined in cpuinfo_x86 structure.
This patch moves the phys_proc_id and cpu_core_id for each processor to
cpuinfo_x86 structure as well.
Jon Mason [Mon, 26 Jun 2006 11:58:14 +0000 (13:58 +0200)]
[PATCH] x86_64: Calgary IOMMU - Calgary specific bits
This patch hooks Calgary into the build, the x86-64 IOMMU
initialization paths, and introduces the Calgary specific bits. The
implementation draws inspiration from both PPC (which has support for
the same chip but requires firmware support which we don't have on
x86-64) and gart. Calgary is different from gart in that it support a
translation table per PHB, as opposed to the single gart aperture.
Changes from previous version:
* Addition of boot-time disablement for bus-level translation/isolation
(e.g, enable userspace DMA for things like X)
* Usage of newer IOMMU abstraction functions
This patch creates a new interface for IOMMUs by adding a centralized
location for IOMMU allocation (for translation tables/apertures) and
IOMMU initialization. In creating these, code was moved around for
abstraction, uniformity, and consiceness.
Take note of the move of the iommu_setup bootarg parsing code to
__setup. This is enabled by moving back the location of the aperture
allocation/detection to mem init (which while ugly, was already the
location of the swiotlb_init).
While a slight departure from the previous patch, I belive this provides
the true intention of the previous versions of the patch which changed
this code. It also makes the addition of the upcoming calgary code much
cleaner than previous patches.
[AK: Removed one broken change. iommu_setup still has to be called
early]
swiotlb relies on the gart specific iommu_aperture variable to know if
we discovered a hardware IOMMU before swiotlb initialization. Introduce
iommu_detected to do the same thing, but in a HW IOMMU neutral manner,
in preparation for adding the Calgary HW IOMMU.
Jan Beulich [Mon, 26 Jun 2006 11:57:41 +0000 (13:57 +0200)]
[PATCH] i386: reliable stack trace support (i386)
These are the i386-specific pieces to enable reliable stack traces. This is
going to be even more useful once CFI annotations get added to he assembly
code, namely to entry.S.
Jan Beulich [Mon, 26 Jun 2006 11:57:38 +0000 (13:57 +0200)]
[PATCH] x86_64: reliable stack trace support (x86-64 syscall
Adjust the CFA offset for 64- and 32-bit syscall entries so that the five
slots pre-subtracted from the stack pointer do not appear to reside outside
of the current frame.
Jan Beulich [Mon, 26 Jun 2006 11:57:32 +0000 (13:57 +0200)]
[PATCH] x86_64: reliable stack trace support (x86-64)
These are the x86_64-specific pieces to enable reliable stack traces. The
only restriction with this is that it currently cannot unwind across the
interrupt->normal stack boundary, as that transition is lacking proper
annotation.
Jan Beulich [Mon, 26 Jun 2006 11:57:28 +0000 (13:57 +0200)]
[PATCH] x86_64: reliable stack trace support
These are the generic bits needed to enable reliable stack traces based
on Dwarf2-like (.eh_frame) unwind information. Subsequent patches will
enable x86-64 and i386 to make use of this.
Thanks to Andi Kleen and Ingo Molnar, who pointed out several possibilities
for improvement.
bibo,mao [Mon, 26 Jun 2006 11:57:25 +0000 (13:57 +0200)]
[PATCH] x86_64: x86_86 msi miss one entry handler
In x86_64 architecture, if device driver with msi function
gets 0xee vector by assign_irq_vector() function, system will
crash if this interrupt happens. It is because 0xee interrupt
entry is empty. This patch modifies this. This patch is based
on 2.6.17-rc6.
Andi Kleen [Mon, 26 Jun 2006 11:57:22 +0000 (13:57 +0200)]
[PATCH] x86_64: Rename IOMMU option, fix help and mark option embedded.
- Rename the GART_IOMMU option to IOMMU to make clear it's not
just for AMD
- Rewrite the help text to better emphatise this fact
- Make it an embedded option because too many people get it wrong.
To my astonishment I discovered the aacraid driver tests this
symbol directly. This looks quite broken to me - it's an internal
implementation detail of the PCI DMA API. Can the maintainer
please clarify what this test was intended to do?
Ingo Molnar [Mon, 26 Jun 2006 11:57:16 +0000 (13:57 +0200)]
[PATCH] x86_64: fix vector_lock deadlock in io_apic.c
Fix a potential deadlock scenario introduced by io_apic.c's new vector_lock
on i386 and x86_64.
Found by the locking correctness validator. The patch was boot-tested on
x86. For details of the deadlock scenario, see the validator output:
======================================================
[ BUG: hard-safe -> hard-unsafe lock order detected! ]
------------------------------------------------------
idle/1 [HC0[0]:SC0[0]:HE0:SE1] is trying to acquire:
(msi_lock){....}, at: [<c04ff8d2>] startup_msi_irq_wo_maskbit+0x10/0x35
and this task is already holding:
(&irq_desc[i].lock){++..}, at: [<c015b924>] probe_irq_on+0x36/0x107
which would create a new lock dependency:
(&irq_desc[i].lock){++..} -> (msi_lock){....}
but this new dependency connects a hard-irq-safe lock:
(&irq_desc[i].lock){++..}
... which became hard-irq-safe at:
[<c01468c4>] lockdep_acquire+0x68/0x84
[<c10485e9>] _spin_lock+0x21/0x2f
[<c015aff5>] __do_IRQ+0x3d/0x113
[<c01062d3>] do_IRQ+0x8c/0xad
to a hard-irq-unsafe lock:
(vector_lock){--..}
... which became hard-irq-unsafe at:
... [<c01468c4>] lockdep_acquire+0x68/0x84
[<c10485e9>] _spin_lock+0x21/0x2f
[<c011b5e8>] assign_irq_vector+0x34/0xc8
[<c1aa82fa>] setup_IO_APIC+0x45a/0xcff
[<c1aa56e3>] smp_prepare_cpus+0x5ea/0x8aa
[<c010033f>] init+0x32/0x2cb
[<c0102005>] kernel_thread_helper+0x5/0xb
which could potentially lead to deadlocks!
other info that might help us debug this:
3 locks held by idle/1:
#0: (port_mutex){--..}, at: [<c067070d>] uart_add_one_port+0x61/0x289
#1: (&state->mutex){--..}, at: [<c067071f>] uart_add_one_port+0x73/0x289
#2: (&irq_desc[i].lock){++..}, at: [<c015b924>] probe_irq_on+0x36/0x107
Jon Mason [Mon, 26 Jun 2006 11:57:13 +0000 (13:57 +0200)]
[PATCH] x86_64: remove unused gart header file
include/asm-x86_64/gart-mapping.h is only ever used in
arch/x86_64/kernel/setup.c and none of its contents are referenced.
Looks to be leftover cruft not removed in the dma_ops patch.
Andi Kleen [Mon, 26 Jun 2006 11:57:07 +0000 (13:57 +0200)]
[PATCH] x86_64: Remove ia32_sys_call_table export
It was originally added for 2.4 oprofile, but 2.6 oprofile doesn't
need that anymore. Shouldn't be any use in tree anymore and it doesn't
make much sense to export the ia32 syscalls when the main syscalls
are not exported.
I think Adrian Bunk asked for removing it several times.
Also included hunk from Adrian to remove the .globl ia32_sys_call_table
Andi Kleen [Mon, 26 Jun 2006 11:56:52 +0000 (13:56 +0200)]
[PATCH] x86_64: Add compat_printk and sysctl to turn off compat layer warnings
Sometimes e.g. with crashme the compat layer warnings can be noisy.
Add a way to turn them off by gating all output through compat_printk
that checks a global sysctl. The default is not changed.
Andi Kleen [Mon, 26 Jun 2006 11:56:40 +0000 (13:56 +0200)]
[PATCH] x86_64: Clean and enhance up K8 northbridge access code
- Factor out the duplicated access/cache code into a single file
* Shared between i386/x86-64.
- Share flush code between AGP and IOMMU
* Fix a bug: AGP didn't wait for end of flush before
- Drop 8 northbridges limit and allocate dynamically
- Add lock to serialize AGP and IOMMU GART flushes
- Add PCI ID for next AMD northbridge
- Random related cleanups
The old K8 NUMA discovery code is unchanged. New systems
should all use SRAT for this.
Cc: "Navin Boppuri" <navin.boppuri@newisys.com> Cc: Dave Jones <davej@redhat.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Jon Mason [Mon, 26 Jun 2006 11:56:37 +0000 (13:56 +0200)]
[PATCH] x86_64: trivial gart clean-up
A trivial change to have gart_unmap_sg call gart_unmap_single directly,
instead of bouncing through the dma_unmap_single wrapper in
dma-mapping.h.
This change required moving the gart_unmap_single above gart_unmap_sg,
and under gart_map_single (which seems a more logical place that its
current location IMHO).
Ingo Molnar [Mon, 26 Jun 2006 11:56:25 +0000 (13:56 +0200)]
[PATCH] x86_64: x86_64-enable-large-bzImage.patch
enable large bzImages on x86_64. (fix is from x86's build.c) Using this
patch i have successfully built and booted an allyesconfig 13MB+ bzImage
on x86_64 too:
Gerd Hoffmann [Mon, 26 Jun 2006 11:56:16 +0000 (13:56 +0200)]
[PATCH] x86_64: x86_64 version of the smp alternative patch.
Changes are largely identical to the i386 version:
* alternative #define are moved to the new alternative.h file.
* one new elf section with pointers to the lock prefixes which can be
nop'ed out for non-smp.
* two new elf sections simliar to the "classic" alternatives to
replace SMP code with simpler UP code.
* fixup headers to use alternative.h instead of defining their own
LOCK / LOCK_PREFIX macros.
The patch reuses the i386 version of the alternatives code to avoid code
duplication. The code in alternatives.c was shuffled around a bit to
reduce the number of #ifdefs needed. It also got some tweaks needed for
x86_64 (vsyscall page handling) and new features (noreplacement option
which was x86_64 only up to now). Debug printk's are changed from
compile-time to runtime.
Loosely based on a early version from Bastian Blank <waldi@debian.org>
Andi Kleen [Mon, 26 Jun 2006 11:56:13 +0000 (13:56 +0200)]
[PATCH] i386/x86-64: Emulate CPUID4 on AMD
Intel systems report the cache level data from CPUID 4 in sysfs.
Add a CPUID 4 emulation for AMD CPUs to report the same
information for them. This allows programs to read this
information in a uniform way.
The AMD way to report this is less flexible so some assumptions
are hardcoded (e.g. no L3)
Andi Kleen [Mon, 26 Jun 2006 11:56:10 +0000 (13:56 +0200)]
[PATCH] i386/x86-64: Use new official CPUID to get APICID/core split on AMD platforms
Previously the apicid<->coreid split was computed based on the max
number of cores. Now use a new CPUID AMD defined for that. On most
systems right now it should be 0 and the old method will be used.
[PATCH] x86_64: Use local APIC ID from local APIC instead of CPUID
vSMPowered systems use apic_cluster too. Forcing apic_physflat works
on these systems too, but only if we change phys_pkg_id to use
hard_smp_prcoessor_id() instead of cpuid_ebx. I am guessing other
multichassi cluster systems would need this too.
Malcolm Parsons [Mon, 26 Jun 2006 01:49:41 +0000 (11:49 +1000)]
[PATCH] uclinux: use PER_LINUX_32BIT in binfmt_flat
binfmt_flat.c calls set_personality with PER_LINUX as the personality.
On the arm architecture this results in the program running in 26bit
usermode. PER_LINUX_32BIT should be used instead. This doesn't affect
other architectures that use binfmt_flat.
[PATCH] m68knommu: improve syscall entry and fix strace
Here is a patch to the system call handling for 5307/5272/etc to:
- fix the strace support (one tested the wrong bit)
- make all system calls a little bit faster by inlining set_esp0 and
supporting ENOSYS out of the critical path.
- remove extraneous spaces
Greg Ungerer [Mon, 26 Jun 2006 01:01:32 +0000 (11:01 +1000)]
[PATCH] m68knommu: force stack alignment on ColdFire
This patch solve a bug triggered by execvp (this function use calloc to
store the argument list and gcc 3.4.x align the stack to word, not to dword).
This situation aren't related to signal handling and all 2.6.x have the bug.
On ColdFire targets we must force the stack to be aligned.
Original patch from Andrea Tarani <andrea.tarani@gilbarco.com>,
Greg Ungerer [Mon, 26 Jun 2006 00:58:09 +0000 (10:58 +1000)]
[PATCH] m68knommu: configurable frequency selection header
Remove list of fixed clock frequency options used for configuring master
clock, and make field an int. Much more flexible this way, no need to add
more options for every new used freqency.
Greg Ungerer [Mon, 26 Jun 2006 00:55:36 +0000 (10:55 +1000)]
[PATCH] m68knommu: configurable frequency selection
Remove list of fixed clock frequency options used for configuring master
clock, and make field an int. Much more flexible this way, no need to add
more options for every new used freqency.
Greg Ungerer [Mon, 26 Jun 2006 00:33:10 +0000 (10:33 +1000)]
[PATCH] m68knommu: cleanup setup.c
A cleanup of m68knommu/kernel/setup.c :
- No need to initialize global pointers to NULL, they will have that value
automatically, and they eat up space in my data segment image in FLASH.
- Remove get_cpuinfo. It has been replaced by show_cpuinfo.
Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Greg Ungerer [Mon, 26 Jun 2006 00:33:10 +0000 (10:33 +1000)]
[PATCH] m68knommu: switch arch config name to CONFIG_M68K
Switch to naming the architecture config options for the m68knommu branch
as "M68K", dropping "M68KNOMMU". The CONFIG_MMU separates the 2 now, and
the m68knommu branch is still strictly speaking an M68K (including the
ColdFire parts).
projects / linux-2.6 / log