Kevin Hilman [Thu, 21 Sep 2006 23:58:57 +0000 (00:58 +0100)]
[ARM] 3856/1: Add clocksource for Intel IXP4xx platforms
Enables the ixp4xx platforms to use Generic time-of-day.
Signed-off-by: Kevin Hilman <khilman@mvista.com> Acked-by: John Stultz <johnstul@us.ibm.com> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Kevin Hilman [Thu, 21 Sep 2006 23:16:30 +0000 (00:16 +0100)]
[ARM] 3855/1: Add generic time support
This patch adds Generic time-of-day support for the ARM architecture.
The support is currently added using #ifdef's so that it can support
sub-arches that do not (yet) have a clocksource added. As sub-arches
add clocksource support, they should 'select GENERIC_TIME'
Signed-off-by: Deepak Saxena <dsaxena@mvista.com> Signed-off-by: Daniel Walker <dwalker@mvista.com> Signed-off-by: Kevin Hilman <khilman@mvista.com> Acked-by: John Stultz <johnstul@us.ibm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
In nommu mode, the exception vector location depends on the platforms.
Some of the implementations may have some special exception control
forwarding method in their ROM/flash and for some of them has its own
re-mapping mechanism by the h/w.
This patch introduces a special configuration CONFIG_CPU_HIGH_VECTOR which
turns on the CR_V bit in nommu mode. The CR_V bit is turned off by default.
This feature depends on CP15 and does not supported by ARM740.
Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.
There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a
dummy abort handler which returns zero for the base restored Data Abort
model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up
for the base updated Data Abort model cores.
Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch removes the static memory mapping for the currently-unused
peripherals [Synchronous Serial, Timer/Counter unit], and for those
drivers that already ioremap() their registers [UART].
Also, the Ethernet driver now uses the platform_device resources but
doesn't yet use ioremap() so we need to pass it the virtual address
instead of the physical address.
Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Andrew Victor [Wed, 27 Sep 2006 15:18:18 +0000 (16:18 +0100)]
[ARM] 3868/1: AT91 hardware header update
This patch adds the hardware register definitions for the TWI (I2C)
controller found on the AT91RM9200 and AT91SAM9xx processors.
It also defines the AIC Fast-Forcing registers added to the AT91SAM9's.
Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Andrew Victor [Wed, 27 Sep 2006 12:23:00 +0000 (13:23 +0100)]
[ARM] 3867/1: AT91 GPIO update
This patch makes the AT91 gpio.c support processor-generic (AT91RM9200
and AT91SAM9xxx). The GPIO controllers supported by a particular AT91
processor are defined in the processor-specific file and are registered
with gpio.c at startup.
Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Andrew Victor [Wed, 27 Sep 2006 09:50:59 +0000 (10:50 +0100)]
[ARM] 3866/1: AT91 clock update
This patch makes the AT91 clock.c support processor-generic (AT91RM9200
and AT91SAM9xxx). The clocks supported by a particular AT91 processor
are defined in the processor-specific file and are registered with
clock.c at startup.
Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Andrew Victor [Wed, 27 Sep 2006 08:44:11 +0000 (09:44 +0100)]
[ARM] 3865/1: AT91RM9200 header updates
This is more preparation for adding support for the new Atmel AT91SAM9
processors.
Changes include:
- Replace AT91_BASE_* with AT91RM9200_BASE_*
- Replace AT91_ID_* with AT91RM9200_ID_*
- ROM, SRAM and UHP address definitions moved to at91rm9200.h.
- The raw AT91_P[ABCD]_* definitions are now depreciated in favour of
the GPIO API.
Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
David Anders [Tue, 26 Sep 2006 16:46:00 +0000 (17:46 +0100)]
[ARM] 3862/2: S3C2410 - add basic power management support for AML M5900 series
this patch registers the wakeup irq, sets a gpio pin to indicate the
status of system for suspend/resume operations, and adds the machine to
the supported machines for use with the simtec-pm
Signed-off-by: David Anders <danders@amltd.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds another hook into sharpsl_pm to notify the machine
specific driver immediately after resume. This is needed to support the Sharp SL-6000 (Tosa).
Signed-off-by: Dirk Opfer <Dirk@Opfer-Online.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The Locomo chip has a SPI interface which is used for SD/MMC cards (only collie).
This patch adds the definition for the SPI device inside the Locomo chip.
Signed-off-by: Dirk Opfer <Dirk@Opfer-Online.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Richard Purdie [Mon, 25 Sep 2006 19:11:48 +0000 (20:11 +0100)]
[ARM] 3847/2: Convert LOMOMO to use struct device for GPIOs
Convert LOMOMO to use struct device * for GPIOs instead of struct
locomo_dev. This enables access to the GPIOs from code which is not
a locomo device itself (such as audio). Access for gpio 31 is removed
for error handling (no such hardware exists).
Signed-off-by: Richard Purdie <rpurdie@rpsys.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 27 Sep 2006 17:00:35 +0000 (18:00 +0100)]
[ARM] Use CPU_CACHE_* where possible in asm/cacheflush.h
Three of the generic cache method options were using explicit CPU
types, whereas they could use the CPU_CACHE_* definitions instead.
Switch them over to use the CPU_CACHE_* definitions.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:
Related operation Safe condition
a. any CP15 access !CPU_CP15
b. alignment trap CPU_CP15_MMU
c. D-cache(C-bit) CPU_CP15
d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
CPU_ARM720 || CPU_ARM740 ||
CPU_XSCALE || CPU_XSC3 )
e. alternate vector CPU_CP15 && !CPU_ARM740
f. TTB CPU_CP15_MMU
g. Domain CPU_CP15_MMU
h. FSR/FAR CPU_CP15_MMU
For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.
Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] nommu: defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU
By merging of uClinux/ARM, we need to treat various CPU cores which have
MMU, MPU or even none for memory management. The memory management
coprocessors are controlled by CP15 register set and the ARM core family
can be categorized by 5 groups by the register ;
G-a. CP15 is MMU : 610, 710, 720, 920, 922, 925, 926, 1020, 1020e, 1022,
v6 and the derivations sa1100, sa110, xscale, xsc3.
G-b. CP15 is MPU : 740, 940, 946, 996, 1156.
G-c. CP15 is MPU or MMU : 1026 (selectable by schematic design)
G-d. CP15 is exist, but nothing for memory managemnt : 966, 968.
G-e. no-CP15 : 7tdmi, 9tdmi, 9e, 9ej
This patch defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU. Thus the
family can be defined as :
- CPU_CP15 only : G-d
- CPU_CP15_MMU(implies CPU_CP15) : G-a, G-c(selectable)
- CPU_CP15_MPU(implies CPU_CP15) : G-b, G-c(selectable)
- !CPU_CP15 : G-e
Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 27 Sep 2006 15:13:48 +0000 (16:13 +0100)]
[ARM] do_bad_area() always takes current and current->active_mm
Since do_bad_area() always takes the currently active task and
(supposed to) take the currently active MM, there's no point passing
them to this function. Instead, obtain references to them inside
do_bad_area().
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 27 Sep 2006 14:38:34 +0000 (15:38 +0100)]
[ARM] Move rest of MMU setup code from mm-armv.c to mmu.c
If we're going to have mmu.c for code which is specific to the MMU
machines, we might as well move the other MMU initialisation
specific code from mm-armv.c into this new file. This also allows
us to make some functions static.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Paul Brook [Sun, 24 Sep 2006 15:54:40 +0000 (16:54 +0100)]
[ARM] 3860/1: Versatile PCI config byte accesses
The ARM Versatile board PCI config space read routines are broken for byte
accesses. The access uses a byte read, so masking the bottom two bits of the
address is wrong.
I guess this is a cut/paste error from the the halfword code which uses
aligned word access+shift+mask.
Signed-off-by: Paul Brook <paul@codesourcery.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The ARM XIP_KERNEL map created in devicemaps_init() is wrong.
The map.pfn is rounded down to an even 1MiB section boundary
which results in va/pa translations errors when XIP_PHYS_ADDR
starts on an odd 1MiB boundary and this causes the kernel to
hang. This patch fixes ARM XIP_KERNEL translation errors for
the odd 1MiB XIP_PHYS_ADDR boundary case.
Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
David Anders [Thu, 21 Sep 2006 21:57:12 +0000 (22:57 +0100)]
[ARM] 3854/2: S3C2410 - add machine type for AML M5900 series (resubmitted)
Add the AML M5900 series to the list of supported machines in the
arch/arm/mach-s3c2410 directory. This ensures the core peripherals
are registered, and the timer source is configured. if selected in
the kernel config the framebuffer registers and mtd partition
information are set. This version of the patch has corrected
formatting and removed the legacy procfs directory entry.
Signed-off-by: David Anders <danders@amltd.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: OMAP: GPIO: IRQSTATUS2 workaround for retention state
In OMAP2420, an incoming GPIO interrupt always sets both GPIO_IRQSTATUS1
and GPIO_IRQSTATUS2, even if the relevant bit is disabled in
GPIO_IRQENABLE1/2 and DSP doesn't use GPIO at all. GPIO_IRQSTATUS1
is for MPU and GPIO_IRQSTATUS2 is for DSP. If IRQSTATUS is set, this
will prevent the system from going to idle state. This patch also clears
IRQSTATUS2 to avoid the above situation.
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Juha Yrjola [Mon, 25 Sep 2006 09:41:43 +0000 (12:41 +0300)]
ARM: OMAP: Add support for forcing osc_ck on
Some boards might use the oscillator clock for powering
external peripherals. Add support for making sure osc_ck
stays active even when trying to go to sleep.
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Timo Teras [Mon, 25 Sep 2006 09:41:42 +0000 (12:41 +0300)]
ARM: OMAP: Add enable/disable functions for dmtimer
Add enable/disable functions which effectively control the GPT iclk and fclk.
Signed-off-by: Timo Teras <timo.teras@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Komal Shah [Mon, 25 Sep 2006 09:41:39 +0000 (12:41 +0300)]
ARM: OMAP: Remove IVA IRQ bank
ARM11 can't access the IVA interrupt controller from
IVA slave port.
From Richard Woodruff:
"The 0x40000000 is an IVA-ARM7 local bus address.
The IVA-INTC is NOT accessible through the IVA-L3-Slave Port.
The current TRM does say this directly and indirectly in a few spots and
in figures."
Signed-off-by: Komal Shah <komal_shah802003@yahoo.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Juha Yrjola [Mon, 25 Sep 2006 09:41:37 +0000 (12:41 +0300)]
ARM: OMAP: Add write memory barriers to OMAP2 clock code
After adjusting clock parameters, OMAP2 CPUs need a memory
barrier to make sure the changes go into effect immediately.
Otherwise bad things will happen if we try to access the
peripheral whose clock is just being enabled.
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Samuel Ortiz [Mon, 25 Sep 2006 09:41:36 +0000 (12:41 +0300)]
ARM: OMAP: Fix OMAP2 clock.c typo
A forgotten parenthesis in clock.c caused the PLL stabilization loop
to not be executed correctly.
Signed-off-by: Samuel Ortiz <samuel.ortiz@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Timo Teras [Mon, 25 Sep 2006 09:41:35 +0000 (12:41 +0300)]
ARM: OMAP: Use GPT iclk only when needed
This patch makes the OMAP2 dmtimers module using the interface
clocks only while the registers are accessed (except GPT1 which has
iclk enabled all the time).
Signed-off-by: Timo Teras <timo.teras@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Imre Deak [Mon, 25 Sep 2006 09:41:33 +0000 (12:41 +0300)]
ARM: OMAP2: Dynamic allocator for GPMC memory space
Add support for assigning memory regions dynamically to peripherals
attached to GPMC interface. Platform specific code should now call
gpmc_cs_request to get a free GPMC memory region instead of using
a fixed address.
Make the H4 and Apollon platform initialization use the new API.
Signed-off-by: Imre Deak <imre.deak@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP: Add some extra #defines for Amstrad Delta
This patch adds some further #defines regarding GPIOs and latch bits for
the Amstrad Delta; the drivers that use them will be submitted at a
later date but there's no reason not to have the information already
there and available for use.
Signed-off-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP: Fix OMAP1 compilation after MPUIO check change
The recent MPUIO range change fix breaks compilation if
CONFIG_ARCH_OMAP24XX isn't defined; it should be OMAP_MAX_GPIO_LINES not
MAX_GPIO_LINES I believe. This one liner fixes it.
Signed-off-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Tony Lindgren <tony@atomide.com>
Mark Howell [Mon, 25 Sep 2006 09:41:29 +0000 (12:41 +0300)]
ARM: OMAP: mux: add config for 16xx SPI pins
This patch adds pin mux info for the SPI master/slave interface on
OMAP16xx. Data from OMAP 1611/1612 TRM and errata. Works for me on my
1611/H2 with current git kernel.
Signed-off-by: Mark Howell <mhowell@northlink.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Imre Deak [Mon, 25 Sep 2006 09:41:28 +0000 (12:41 +0300)]
ARM: OMAP: Sleep is prevented when no LCD is attached
We have to make sure that the LCD DMA external destination bit is
cleared by default, otherwise OMAP won't sleep.
Signed-off-by: Imre Deak <imre.deak@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Imre Deak [Mon, 25 Sep 2006 09:41:27 +0000 (12:41 +0300)]
ARM: OMAP: GPIO: fix MPUIO check
- MPUIO doesn't exist on OMAP2
- no error was returned for too big MPUIO numbers
Signed-off-by: Imre Deak <imre.deak@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Samuel Ortiz [Mon, 25 Sep 2006 09:41:22 +0000 (12:41 +0300)]
ARM: OMAP: Added OMAP24xx camera IRQ definition
Signed-off-by: Samuel Ortiz <samuel.ortiz@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Imre Deak [Mon, 25 Sep 2006 09:41:21 +0000 (12:41 +0300)]
ARM: OMAP: timer32k: fix tick count calculation when reprogramming
Reprogramming takes places before putting the CPU into idle mode if
the dynamic tick option is enabled. The timer is then set to expire
at the next pending timer event. Because some time has already passed
since the last reported jiffy we have to wait less than the time
specified in jiffies.
Also make sure we don't set a load value of 0 whose outcome is
unspecified according to the TRM.
Signed-off-by: Imre Deak <imre.deak@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
- Document the meaning for OP_SCALAR, OP_SD and add OP_DD.
- Formatting cleanups
- Remove now redundant code for making compare instructions
operate on scalar values.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Gen FUKATSU [Thu, 21 Sep 2006 13:08:24 +0000 (14:08 +0100)]
[ARM] 3789/4: Fix VFP emulation to ignore VECITR for scalar instruction
VECITR in Floating-Point Exception register indicates the number of
remaining short vector iterations after a potential exception was
detected.
In case of exception caused by scalar instructions, VECITR is NOT updated.
Therefore emulation for VFP must ignore VECITR field
and treat "veclen" as zero when recognizing scalar instructing.
Signed-off-by: Gen Fukatsu <fukatsu.gen@jp.panasonic.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Dan Fandrich [Wed, 20 Sep 2006 22:28:51 +0000 (23:28 +0100)]
[ARM] 3792/2: Fix description of ZBOOT_ROM_BSS
The documentation for the ZBOOT_ROM_BSS config option describes it as
"The base address of 64KiB of read/write memory in the target for the
ROM-able zImage..." In actuality, it requires more than 100 KiB of
space in addition to enough space to hold the decompressed kernel.
This patch fixes the description in the Kconfig file.
Signed-off-by: Dan Fandrich <dfandrich@intrinsyc.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
George G. Davis [Thu, 21 Sep 2006 02:57:04 +0000 (03:57 +0100)]
[ARM] 3853/1: Fix flush_ptrace_access() thinko for nonaliasing VIPT cache case
Fix thinko in the flush_ptrace_access() "if (expr)" for the ARM
VIPT non-aliasing cache case. We only need to flush cache when
VM_EXEC is set in vma->vm_flags but "if (expr) always evaluates
to true on UP systems for the ARM VIPT non-aliasing cache case.
Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] 3851/1: iop3xx: add io-data glantank support
Add support for the IO-Data GLAN Tank, from Martin Michlmayr.
Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Ben Dooks [Wed, 20 Sep 2006 20:57:06 +0000 (21:57 +0100)]
[ARM] 3846/1: S3C24XX: Fix osiris memory map
The memory mapping for the Osiris machine
are all off by one bit, and the base address
has been fixed for writing (bit25 is being
checked by the write, but not on read)
Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Ben Dooks [Wed, 20 Sep 2006 19:32:33 +0000 (20:32 +0100)]
[ARM] 3840/1: S3C2412: Add machine VSTMS
Add new machine VSTMS
Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Thomas Gleixner <tglx@linuxtronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since the iop32x code isn't iop321-specific, and the iop33x code isn't
iop331-specfic, do a s/iop321/iop32x/ and s/iop331/iop33x/, and tidy up
the code to conform to the coding style guidelines somewhat better.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Revamp the iop3xx board support: move the support code for each iop
board type into its own file, start using platform serial and platform
physmap flash devices, switch to a per-board time tick rate, and get
rid of the ARCH_EP80219 and STEPD config options by doing the relevant
checks at run time.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] 3825/1: iop3xx: use cp6 enable/disable macros
Add CP6 enable/disable sequences to the timekeeping code and the IRQ
code. As a result, we can't depend on CP6 access being enabled when
we enter get_irqnr_and_base anymore, so switch the latter over to
using memory-mapped accesses for now.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add macros to enable and disable access to CP6. On the iop3xx, enabling
CP6 access unfortunately also enables access to that coprocessor from
unprivileged code, so we need these macros to enable and disable access
to the coprocessor whenever we need to access it.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
projects / linux-2.6 / log