From: Robin Getz Date: Sun, 5 Aug 2007 09:21:55 +0000 (+0800) Subject: Blackfin arch: fix the aliased write macros X-Git-Tag: v2.6.23-rc7~44^2~1 X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e62687f995fd7ba0b68c3b0a4f4d9fd9d1c54ec2;p=linux-2.6 Blackfin arch: fix the aliased write macros Signed-off-by: Robin Getz Signed-off-by: Bryan Wu --- diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index 6e87ab269f..73d4d65249 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h @@ -83,9 +83,9 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ #define bfin_read_SWRST() bfin_read_SICA_SWRST() -#define bfin_write_SWRST() bfin_write_SICA_SWRST() +#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val) #define bfin_read_SYSCR() bfin_read_SICA_SYSCR() -#define bfin_write_SYSCR() bfin_write_SICA_SYSCR() +#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val) /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ #define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)