From: Kevin D. Kissell <kevink@mips.com>
Date: Fri, 27 Jul 2007 17:45:25 +0000 (+0100)
Subject: [MIPS] SMTC: Safety net for i8259A interrupts.
X-Git-Tag: v2.6.23-rc2~30^2~36
X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c3a005f4b6a7752608e75d016ef8d07c55285e48;p=linux-2.6

[MIPS] SMTC: Safety net for i8259A interrupts.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index c78d483496..97aeb8c4e6 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -330,6 +330,18 @@ void __init arch_init_irq(void)
 			(0x100 << MIPSCPU_INT_I8259A));
 		setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
 			&corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
+		/*
+		 * Temporary hack to ensure that the subsidiary device
+		 * interrupts coing in via the i8259A, but associated
+		 * with low IRQ numbers, will restore the Status.IM
+		 * value associated with the i8259A.
+		 */
+		{
+			int i;
+
+			for (i = 0; i < 16; i++)
+				irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
+		}
 #else /* Not SMTC */
 		setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
 		setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);