From: Stefan Roese Date: Mon, 5 May 2008 06:53:19 +0000 (+1000) Subject: [POWERPC] 4xx: Fix problem with new TLB storage attibute fields on 440x6 core X-Git-Tag: v2.6.26-rc2~16^2~7^2~2 X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=a96df496ed1496f3e52a9b3c860cf967aa48adda;p=linux-2.6 [POWERPC] 4xx: Fix problem with new TLB storage attibute fields on 440x6 core The new 440x6 core used on AMCC 460EX/GT introduces new storage attibure fields to the TLB2 word. Those are: Bit 11 12 13 14 15 WL1 IL1I IL1D IL2I IL2D With these bits the cache (L1 and L2) can be configured in a more flexible way, instruction- and data-cache independently now. The "old" I and W bits are still available and setting these old bits will automically set these new bits too (for backward compatibilty). The current code does not clear these fields resulting in disabling the cache by chance. This patch now makes sure that these new bits are cleared when the TLB2 word is written. Signed-off-by: Stefan Roese Signed-off-by: Josh Boyer --- diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index b84ec6a2fc..c2b9dc4fce 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -653,7 +653,14 @@ finish_tlb_load: rlwimi r10, r11, 0, 26, 26 /* UX = HWEXEC & USER */ rlwimi r12, r10, 0, 26, 31 /* Insert static perms */ - rlwinm r12, r12, 0, 20, 15 /* Clear U0-U3 */ + + /* + * Clear U0-U3 and WL1 IL1I IL1D IL2I IL2D bits which are added + * on newer 440 cores like the 440x6 used on AMCC 460EX/460GT (see + * include/asm-powerpc/pgtable-ppc32.h for details). + */ + rlwinm r12, r12, 0, 20, 10 + tlbwe r12, r13, PPC44x_TLB_ATTRIB /* Write ATTRIB */ /* Done...restore registers and get out of here. diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h index 7c97b5a08d..c08e714d0c 100644 --- a/include/asm-powerpc/pgtable-ppc32.h +++ b/include/asm-powerpc/pgtable-ppc32.h @@ -209,6 +209,13 @@ extern int icache_44x_need_flush; * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR * + * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional + * TLB2 storage attibute fields. Those are: + * + * TLB2: + * 0...10 11 12 13 14 15 16...31 + * no change WL1 IL1I IL1D IL2I IL2D no change + * * There are some constrains and options, to decide mapping software bits * into TLB entry. *