From: Lennert Buytenhek Date: Thu, 27 Mar 2008 18:51:41 +0000 (-0400) Subject: Orion: orion -> orion5x rename X-Git-Tag: v2.6.26-rc1~1131^2~2^9~3 X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=9dd0b194bf6804b1998f0fe261b2606ec7b58d72;p=linux-2.6 Orion: orion -> orion5x rename Do a global s/orion/orion5x/ of the Orion 5x-specific bits (i.e. not the plat-orion bits.) Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Saeed Bishara Acked-by: Russell King Signed-off-by: Nicolas Pitre --- diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 845f96e9f0..2f4fb773f3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -377,7 +377,7 @@ config ARCH_MXC help Support for Freescale MXC/iMX-based family of processors -config ARCH_ORION +config ARCH_ORION5X bool "Marvell Orion" depends on MMU select PCI @@ -386,7 +386,8 @@ config ARCH_ORION select GENERIC_CLOCKEVENTS select PLAT_ORION help - Support for Marvell Orion System on Chip family. + Support for the following Marvell Orion 5x series SoCs: + Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.) config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" @@ -517,7 +518,7 @@ source "arch/arm/mach-omap1/Kconfig" source "arch/arm/mach-omap2/Kconfig" -source "arch/arm/mach-orion/Kconfig" +source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 27866cf0c1..6f99750537 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -139,7 +139,7 @@ endif machine-$(CONFIG_ARCH_KS8695) := ks8695 incdir-$(CONFIG_ARCH_MXC) := mxc machine-$(CONFIG_ARCH_MX3) := mx3 - machine-$(CONFIG_ARCH_ORION) := orion + machine-$(CONFIG_ARCH_ORION5X) := orion5x machine-$(CONFIG_ARCH_MSM7X00A) := msm ifeq ($(CONFIG_ARCH_EBSA110),y) diff --git a/arch/arm/configs/orion_defconfig b/arch/arm/configs/orion5x_defconfig similarity index 99% rename from arch/arm/configs/orion_defconfig rename to arch/arm/configs/orion5x_defconfig index 1e5aaa645f..52cd99bd52 100644 --- a/arch/arm/configs/orion_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -140,7 +140,7 @@ CONFIG_CLASSIC_RCU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_MXC is not set -CONFIG_ARCH_ORION=y +CONFIG_ARCH_ORION5X=y # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h deleted file mode 100644 index bcc31adaca..0000000000 --- a/arch/arm/mach-orion/common.h +++ /dev/null @@ -1,72 +0,0 @@ -#ifndef __ARCH_ORION_COMMON_H -#define __ARCH_ORION_COMMON_H - -/* - * Basic Orion init functions used early by machine-setup. - */ - -void orion_map_io(void); -void orion_init_irq(void); -void orion_init(void); -extern struct sys_timer orion_timer; - -/* - * Enumerations and functions for Orion windows mapping. Used by Orion core - * functions to map its interfaces and by the machine-setup to map its on- - * board devices. Details in /mach-orion/addr-map.c - */ -extern struct mbus_dram_target_info orion_mbus_dram_info; -void orion_setup_cpu_mbus_bridge(void); -void orion_setup_dev_boot_win(u32 base, u32 size); -void orion_setup_dev0_win(u32 base, u32 size); -void orion_setup_dev1_win(u32 base, u32 size); -void orion_setup_dev2_win(u32 base, u32 size); -void orion_setup_pcie_wa_win(u32 base, u32 size); -void orion_setup_eth_wins(void); - -/* - * Shared code used internally by other Orion core functions. - * (/mach-orion/pci.c) - */ - -struct pci_sys_data; -struct pci_bus; - -void orion_pcie_id(u32 *dev, u32 *rev); -int orion_pcie_local_bus_nr(void); -int orion_pci_local_bus_nr(void); -int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); -struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); - -/* - * Valid GPIO pins according to MPP setup, used by machine-setup. - * (/mach-orion/gpio.c). - */ - -void orion_gpio_set_valid_pins(u32 pins); -void gpio_display(void); /* debug */ - -/* - * Pull in Orion Ethernet platform_data, used by machine-setup - */ - -struct mv643xx_eth_platform_data; - -void orion_eth_init(struct mv643xx_eth_platform_data *eth_data); - -/* - * Orion Sata platform_data, used by machine-setup - */ - -struct mv_sata_platform_data; - -void orion_sata_init(struct mv_sata_platform_data *sata_data); - -struct machine_desc; -struct meminfo; -struct tag; -extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, - char **, struct meminfo *); - - -#endif diff --git a/arch/arm/mach-orion/Kconfig b/arch/arm/mach-orion5x/Kconfig similarity index 98% rename from arch/arm/mach-orion/Kconfig rename to arch/arm/mach-orion5x/Kconfig index 1dcbb6ac5a..01c66957d8 100644 --- a/arch/arm/mach-orion/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -1,4 +1,4 @@ -if ARCH_ORION +if ARCH_ORION5X menu "Orion Implementations" diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion5x/Makefile similarity index 100% rename from arch/arm/mach-orion/Makefile rename to arch/arm/mach-orion5x/Makefile diff --git a/arch/arm/mach-orion/Makefile.boot b/arch/arm/mach-orion5x/Makefile.boot similarity index 100% rename from arch/arm/mach-orion/Makefile.boot rename to arch/arm/mach-orion5x/Makefile.boot diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion5x/addr-map.c similarity index 59% rename from arch/arm/mach-orion/addr-map.c rename to arch/arm/mach-orion5x/addr-map.c index 738de617e3..6b179371e0 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -1,7 +1,7 @@ /* - * arch/arm/mach-orion/addr-map.c + * arch/arm/mach-orion5x/addr-map.c * - * Address map functions for Marvell Orion System On Chip + * Address map functions for Marvell Orion 5x SoCs * * Maintainer: Tzachi Perelstein * @@ -29,7 +29,7 @@ * Setup access to PCI and PCI-E IO/MEM space is issued by this file. * Setup access to various devices located on the device bus interface (e.g. * flashes, RTC, etc) should be issued by machine-setup.c according to - * specific board population (by using orion_setup_*_win()). + * specific board population (by using orion5x_setup_*_win()). * * Non-CPU Masters address decoding -- * Unlike the CPU, we setup the access from Orion's master interfaces to DDR @@ -66,8 +66,8 @@ /* * Helpers to get DDR bank info */ -#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8)) -#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8)) +#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8)) +#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8)) #define DDR_MAX_CS 4 #define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) #define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) @@ -76,30 +76,30 @@ /* * CPU Address Decode Windows registers */ -#define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4)) -#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) -#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) -#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) +#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) +#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) +#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) +#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) /* * Gigabit Ethernet Address Decode Windows registers */ -#define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8)) -#define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8)) -#define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4)) -#define ETH_WIN_EN ORION_ETH_REG(0x290) -#define ETH_WIN_PROT ORION_ETH_REG(0x294) +#define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8)) +#define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8)) +#define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4)) +#define ETH_WIN_EN ORION5X_ETH_REG(0x290) +#define ETH_WIN_PROT ORION5X_ETH_REG(0x294) #define ETH_MAX_WIN 6 #define ETH_MAX_REMAP_WIN 4 -struct mbus_dram_target_info orion_mbus_dram_info; +struct mbus_dram_target_info orion5x_mbus_dram_info; -static int __init orion_cpu_win_can_remap(int win) +static int __init orion5x_cpu_win_can_remap(int win) { u32 dev, rev; - orion_pcie_id(&dev, &rev); + orion5x_pcie_id(&dev, &rev); if ((dev == MV88F5281_DEV_ID && win < 4) || (dev == MV88F5182_DEV_ID && win < 2) || (dev == MV88F5181_DEV_ID && win < 2)) @@ -111,20 +111,20 @@ static int __init orion_cpu_win_can_remap(int win) static void __init setup_cpu_win(int win, u32 base, u32 size, u8 target, u8 attr, int remap) { - orion_write(CPU_WIN_BASE(win), base & 0xffff0000); - orion_write(CPU_WIN_CTRL(win), + orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000); + orion5x_write(CPU_WIN_CTRL(win), ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); - if (orion_cpu_win_can_remap(win)) { + if (orion5x_cpu_win_can_remap(win)) { if (remap < 0) remap = base; - orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); - orion_write(CPU_WIN_REMAP_HI(win), 0); + orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); + orion5x_write(CPU_WIN_REMAP_HI(win), 0); } } -void __init orion_setup_cpu_mbus_bridge(void) +void __init orion5x_setup_cpu_mbus_bridge(void) { int i; int cs; @@ -133,30 +133,30 @@ void __init orion_setup_cpu_mbus_bridge(void) * First, disable and clear windows. */ for (i = 0; i < 8; i++) { - orion_write(CPU_WIN_BASE(i), 0); - orion_write(CPU_WIN_CTRL(i), 0); - if (orion_cpu_win_can_remap(i)) { - orion_write(CPU_WIN_REMAP_LO(i), 0); - orion_write(CPU_WIN_REMAP_HI(i), 0); + orion5x_write(CPU_WIN_BASE(i), 0); + orion5x_write(CPU_WIN_CTRL(i), 0); + if (orion5x_cpu_win_can_remap(i)) { + orion5x_write(CPU_WIN_REMAP_LO(i), 0); + orion5x_write(CPU_WIN_REMAP_HI(i), 0); } } /* * Setup windows for PCI+PCIe IO+MEM space. */ - setup_cpu_win(0, ORION_PCIE_IO_PHYS_BASE, ORION_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, ORION_PCIE_IO_BUS_BASE); - setup_cpu_win(1, ORION_PCI_IO_PHYS_BASE, ORION_PCI_IO_SIZE, - TARGET_PCI, ATTR_PCI_IO, ORION_PCI_IO_BUS_BASE); - setup_cpu_win(2, ORION_PCIE_MEM_PHYS_BASE, ORION_PCIE_MEM_SIZE, + setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); + setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, + TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); + setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, TARGET_PCIE, ATTR_PCIE_MEM, -1); - setup_cpu_win(3, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE, + setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, TARGET_PCI, ATTR_PCI_MEM, -1); /* * Setup MBUS dram target info. */ - orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; for (i = 0, cs = 0; i < 4; i++) { u32 base = readl(DDR_BASE_CS(i)); @@ -168,42 +168,42 @@ void __init orion_setup_cpu_mbus_bridge(void) if (size & 1) { struct mbus_dram_window *w; - w = &orion_mbus_dram_info.cs[cs++]; + w = &orion5x_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0xf & ~(1 << i); w->base = base & 0xff000000; w->size = (size | 0x00ffffff) + 1; } } - orion_mbus_dram_info.num_cs = cs; + orion5x_mbus_dram_info.num_cs = cs; } -void __init orion_setup_dev_boot_win(u32 base, u32 size) +void __init orion5x_setup_dev_boot_win(u32 base, u32 size) { setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); } -void __init orion_setup_dev0_win(u32 base, u32 size) +void __init orion5x_setup_dev0_win(u32 base, u32 size) { setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); } -void __init orion_setup_dev1_win(u32 base, u32 size) +void __init orion5x_setup_dev1_win(u32 base, u32 size) { setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); } -void __init orion_setup_dev2_win(u32 base, u32 size) +void __init orion5x_setup_dev2_win(u32 base, u32 size) { setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); } -void __init orion_setup_pcie_wa_win(u32 base, u32 size) +void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) { setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); } -void __init orion_setup_eth_wins(void) +void __init orion5x_setup_eth_wins(void) { int i; @@ -211,12 +211,12 @@ void __init orion_setup_eth_wins(void) * First, disable and clear windows */ for (i = 0; i < ETH_MAX_WIN; i++) { - orion_write(ETH_WIN_BASE(i), 0); - orion_write(ETH_WIN_SIZE(i), 0); - orion_setbits(ETH_WIN_EN, 1 << i); - orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); + orion5x_write(ETH_WIN_BASE(i), 0); + orion5x_write(ETH_WIN_SIZE(i), 0); + orion5x_setbits(ETH_WIN_EN, 1 << i); + orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); if (i < ETH_MAX_REMAP_WIN) - orion_write(ETH_WIN_REMAP(i), 0); + orion5x_write(ETH_WIN_REMAP(i), 0); } /* @@ -224,17 +224,17 @@ void __init orion_setup_eth_wins(void) */ for (i = 0; i < DDR_MAX_CS; i++) { u32 base, size; - size = orion_read(DDR_SIZE_CS(i)); - base = orion_read(DDR_BASE_CS(i)); + size = orion5x_read(DDR_SIZE_CS(i)); + base = orion5x_read(DDR_BASE_CS(i)); if (size & DDR_BANK_EN) { base = DDR_REG_TO_BASE(base); size = DDR_REG_TO_SIZE(size); - orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); - orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) | + orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); + orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) | (ATTR_DDR_CS(i) << 8) | TARGET_DDR); - orion_clrbits(ETH_WIN_EN, 1 << i); - orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); + orion5x_clrbits(ETH_WIN_EN, 1 << i); + orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); } } } diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion5x/common.c similarity index 57% rename from arch/arm/mach-orion/common.c rename to arch/arm/mach-orion5x/common.c index 85c8f18268..439c7784af 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -1,7 +1,7 @@ /* - * arch/arm/mach-orion/common.c + * arch/arm/mach-orion5x/common.c * - * Core functions for Marvell Orion System On Chip + * Core functions for Marvell Orion 5x SoCs * * Maintainer: Tzachi Perelstein * @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include @@ -34,51 +34,51 @@ /***************************************************************************** * I/O Address Mapping ****************************************************************************/ -static struct map_desc orion_io_desc[] __initdata = { +static struct map_desc orion5x_io_desc[] __initdata = { { - .virtual = ORION_REGS_VIRT_BASE, - .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE), - .length = ORION_REGS_SIZE, + .virtual = ORION5X_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), + .length = ORION5X_REGS_SIZE, .type = MT_DEVICE }, { - .virtual = ORION_PCIE_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE), - .length = ORION_PCIE_IO_SIZE, + .virtual = ORION5X_PCIE_IO_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), + .length = ORION5X_PCIE_IO_SIZE, .type = MT_DEVICE }, { - .virtual = ORION_PCI_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE), - .length = ORION_PCI_IO_SIZE, + .virtual = ORION5X_PCI_IO_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), + .length = ORION5X_PCI_IO_SIZE, .type = MT_DEVICE }, { - .virtual = ORION_PCIE_WA_VIRT_BASE, - .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE), - .length = ORION_PCIE_WA_SIZE, + .virtual = ORION5X_PCIE_WA_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), + .length = ORION5X_PCIE_WA_SIZE, .type = MT_DEVICE }, }; -void __init orion_map_io(void) +void __init orion5x_map_io(void) { - iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc)); + iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); } /***************************************************************************** * UART ****************************************************************************/ -static struct resource orion_uart_resources[] = { +static struct resource orion5x_uart_resources[] = { { .start = UART0_PHYS_BASE, .end = UART0_PHYS_BASE + 0xff, .flags = IORESOURCE_MEM, }, { - .start = IRQ_ORION_UART0, - .end = IRQ_ORION_UART0, + .start = IRQ_ORION5X_UART0, + .end = IRQ_ORION5X_UART0, .flags = IORESOURCE_IRQ, }, { @@ -87,102 +87,102 @@ static struct resource orion_uart_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = IRQ_ORION_UART1, - .end = IRQ_ORION_UART1, + .start = IRQ_ORION5X_UART1, + .end = IRQ_ORION5X_UART1, .flags = IORESOURCE_IRQ, }, }; -static struct plat_serial8250_port orion_uart_data[] = { +static struct plat_serial8250_port orion5x_uart_data[] = { { .mapbase = UART0_PHYS_BASE, .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_ORION_UART0, + .irq = IRQ_ORION5X_UART0, .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = ORION_TCLK, + .uartclk = ORION5X_TCLK, }, { .mapbase = UART1_PHYS_BASE, .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_ORION_UART1, + .irq = IRQ_ORION5X_UART1, .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = ORION_TCLK, + .uartclk = ORION5X_TCLK, }, { }, }; -static struct platform_device orion_uart = { +static struct platform_device orion5x_uart = { .name = "serial8250", .id = PLAT8250_DEV_PLATFORM, .dev = { - .platform_data = orion_uart_data, + .platform_data = orion5x_uart_data, }, - .resource = orion_uart_resources, - .num_resources = ARRAY_SIZE(orion_uart_resources), + .resource = orion5x_uart_resources, + .num_resources = ARRAY_SIZE(orion5x_uart_resources), }; /******************************************************************************* * USB Controller - 2 interfaces ******************************************************************************/ -static struct resource orion_ehci0_resources[] = { +static struct resource orion5x_ehci0_resources[] = { { - .start = ORION_USB0_PHYS_BASE, - .end = ORION_USB0_PHYS_BASE + SZ_4K, + .start = ORION5X_USB0_PHYS_BASE, + .end = ORION5X_USB0_PHYS_BASE + SZ_4K, .flags = IORESOURCE_MEM, }, { - .start = IRQ_ORION_USB0_CTRL, - .end = IRQ_ORION_USB0_CTRL, + .start = IRQ_ORION5X_USB0_CTRL, + .end = IRQ_ORION5X_USB0_CTRL, .flags = IORESOURCE_IRQ, }, }; -static struct resource orion_ehci1_resources[] = { +static struct resource orion5x_ehci1_resources[] = { { - .start = ORION_USB1_PHYS_BASE, - .end = ORION_USB1_PHYS_BASE + SZ_4K, + .start = ORION5X_USB1_PHYS_BASE, + .end = ORION5X_USB1_PHYS_BASE + SZ_4K, .flags = IORESOURCE_MEM, }, { - .start = IRQ_ORION_USB1_CTRL, - .end = IRQ_ORION_USB1_CTRL, + .start = IRQ_ORION5X_USB1_CTRL, + .end = IRQ_ORION5X_USB1_CTRL, .flags = IORESOURCE_IRQ, }, }; -static struct orion_ehci_data orion_ehci_data = { - .dram = &orion_mbus_dram_info, +static struct orion_ehci_data orion5x_ehci_data = { + .dram = &orion5x_mbus_dram_info, }; static u64 ehci_dmamask = 0xffffffffUL; -static struct platform_device orion_ehci0 = { +static struct platform_device orion5x_ehci0 = { .name = "orion-ehci", .id = 0, .dev = { .dma_mask = &ehci_dmamask, .coherent_dma_mask = 0xffffffff, - .platform_data = &orion_ehci_data, + .platform_data = &orion5x_ehci_data, }, - .resource = orion_ehci0_resources, - .num_resources = ARRAY_SIZE(orion_ehci0_resources), + .resource = orion5x_ehci0_resources, + .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), }; -static struct platform_device orion_ehci1 = { +static struct platform_device orion5x_ehci1 = { .name = "orion-ehci", .id = 1, .dev = { .dma_mask = &ehci_dmamask, .coherent_dma_mask = 0xffffffff, - .platform_data = &orion_ehci_data, + .platform_data = &orion5x_ehci_data, }, - .resource = orion_ehci1_resources, - .num_resources = ARRAY_SIZE(orion_ehci1_resources), + .resource = orion5x_ehci1_resources, + .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), }; /***************************************************************************** @@ -190,42 +190,42 @@ static struct platform_device orion_ehci1 = { * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) ****************************************************************************/ -static struct resource orion_eth_shared_resources[] = { +static struct resource orion5x_eth_shared_resources[] = { { - .start = ORION_ETH_PHYS_BASE + 0x2000, - .end = ORION_ETH_PHYS_BASE + 0x3fff, + .start = ORION5X_ETH_PHYS_BASE + 0x2000, + .end = ORION5X_ETH_PHYS_BASE + 0x3fff, .flags = IORESOURCE_MEM, }, }; -static struct platform_device orion_eth_shared = { +static struct platform_device orion5x_eth_shared = { .name = MV643XX_ETH_SHARED_NAME, .id = 0, .num_resources = 1, - .resource = orion_eth_shared_resources, + .resource = orion5x_eth_shared_resources, }; -static struct resource orion_eth_resources[] = { +static struct resource orion5x_eth_resources[] = { { .name = "eth irq", - .start = IRQ_ORION_ETH_SUM, - .end = IRQ_ORION_ETH_SUM, + .start = IRQ_ORION5X_ETH_SUM, + .end = IRQ_ORION5X_ETH_SUM, .flags = IORESOURCE_IRQ, } }; -static struct platform_device orion_eth = { +static struct platform_device orion5x_eth = { .name = MV643XX_ETH_NAME, .id = 0, .num_resources = 1, - .resource = orion_eth_resources, + .resource = orion5x_eth_resources, }; -void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) +void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) { - orion_eth.dev.platform_data = eth_data; - platform_device_register(&orion_eth_shared); - platform_device_register(&orion_eth); + orion5x_eth.dev.platform_data = eth_data; + platform_device_register(&orion5x_eth_shared); + platform_device_register(&orion5x_eth); } /***************************************************************************** @@ -233,13 +233,13 @@ void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) * (The Orion and Discovery (MV643xx) families share the same I2C controller) ****************************************************************************/ -static struct mv64xxx_i2c_pdata orion_i2c_pdata = { +static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { .freq_m = 8, /* assumes 166 MHz TCLK */ .freq_n = 3, .timeout = 1000, /* Default timeout of 1 second */ }; -static struct resource orion_i2c_resources[] = { +static struct resource orion5x_i2c_resources[] = { { .name = "i2c base", .start = I2C_PHYS_BASE, @@ -248,68 +248,68 @@ static struct resource orion_i2c_resources[] = { }, { .name = "i2c irq", - .start = IRQ_ORION_I2C, - .end = IRQ_ORION_I2C, + .start = IRQ_ORION5X_I2C, + .end = IRQ_ORION5X_I2C, .flags = IORESOURCE_IRQ, }, }; -static struct platform_device orion_i2c = { +static struct platform_device orion5x_i2c = { .name = MV64XXX_I2C_CTLR_NAME, .id = 0, - .num_resources = ARRAY_SIZE(orion_i2c_resources), - .resource = orion_i2c_resources, + .num_resources = ARRAY_SIZE(orion5x_i2c_resources), + .resource = orion5x_i2c_resources, .dev = { - .platform_data = &orion_i2c_pdata, + .platform_data = &orion5x_i2c_pdata, }, }; /***************************************************************************** * Sata port ****************************************************************************/ -static struct resource orion_sata_resources[] = { +static struct resource orion5x_sata_resources[] = { { .name = "sata base", - .start = ORION_SATA_PHYS_BASE, - .end = ORION_SATA_PHYS_BASE + 0x5000 - 1, + .start = ORION5X_SATA_PHYS_BASE, + .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, .flags = IORESOURCE_MEM, }, { .name = "sata irq", - .start = IRQ_ORION_SATA, - .end = IRQ_ORION_SATA, + .start = IRQ_ORION5X_SATA, + .end = IRQ_ORION5X_SATA, .flags = IORESOURCE_IRQ, }, }; -static struct platform_device orion_sata = { +static struct platform_device orion5x_sata = { .name = "sata_mv", .id = 0, .dev = { .coherent_dma_mask = 0xffffffff, }, - .num_resources = ARRAY_SIZE(orion_sata_resources), - .resource = orion_sata_resources, + .num_resources = ARRAY_SIZE(orion5x_sata_resources), + .resource = orion5x_sata_resources, }; -void __init orion_sata_init(struct mv_sata_platform_data *sata_data) +void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) { - sata_data->dram = &orion_mbus_dram_info; - orion_sata.dev.platform_data = sata_data; - platform_device_register(&orion_sata); + sata_data->dram = &orion5x_mbus_dram_info; + orion5x_sata.dev.platform_data = sata_data; + platform_device_register(&orion5x_sata); } /***************************************************************************** * Time handling ****************************************************************************/ -static void orion_timer_init(void) +static void orion5x_timer_init(void) { - orion_time_init(IRQ_ORION_BRIDGE, ORION_TCLK); + orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK); } -struct sys_timer orion_timer = { - .init = orion_timer_init, +struct sys_timer orion5x_timer = { + .init = orion5x_timer_init, }; /***************************************************************************** @@ -319,9 +319,9 @@ struct sys_timer orion_timer = { /* * Identify device ID and rev from PCIE configuration header space '0'. */ -static void __init orion_id(u32 *dev, u32 *rev, char **dev_name) +static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) { - orion_pcie_id(dev, rev); + orion5x_pcie_id(dev, rev); if (*dev == MV88F5281_DEV_ID) { if (*rev == MV88F5281_REV_D2) { @@ -348,28 +348,28 @@ static void __init orion_id(u32 *dev, u32 *rev, char **dev_name) } } -void __init orion_init(void) +void __init orion5x_init(void) { char *dev_name; u32 dev, rev; - orion_id(&dev, &rev, &dev_name); - printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK); + orion5x_id(&dev, &rev, &dev_name); + printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK); /* * Setup Orion address map */ - orion_setup_cpu_mbus_bridge(); - orion_setup_eth_wins(); + orion5x_setup_cpu_mbus_bridge(); + orion5x_setup_eth_wins(); /* * Register devices. */ - platform_device_register(&orion_uart); - platform_device_register(&orion_ehci0); + platform_device_register(&orion5x_uart); + platform_device_register(&orion5x_ehci0); if (dev == MV88F5182_DEV_ID) - platform_device_register(&orion_ehci1); - platform_device_register(&orion_i2c); + platform_device_register(&orion5x_ehci1); + platform_device_register(&orion5x_i2c); } /* diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h new file mode 100644 index 0000000000..f4c4c9a72a --- /dev/null +++ b/arch/arm/mach-orion5x/common.h @@ -0,0 +1,72 @@ +#ifndef __ARCH_ORION5X_COMMON_H +#define __ARCH_ORION5X_COMMON_H + +/* + * Basic Orion init functions used early by machine-setup. + */ + +void orion5x_map_io(void); +void orion5x_init_irq(void); +void orion5x_init(void); +extern struct sys_timer orion5x_timer; + +/* + * Enumerations and functions for Orion windows mapping. Used by Orion core + * functions to map its interfaces and by the machine-setup to map its on- + * board devices. Details in /mach-orion/addr-map.c + */ +extern struct mbus_dram_target_info orion5x_mbus_dram_info; +void orion5x_setup_cpu_mbus_bridge(void); +void orion5x_setup_dev_boot_win(u32 base, u32 size); +void orion5x_setup_dev0_win(u32 base, u32 size); +void orion5x_setup_dev1_win(u32 base, u32 size); +void orion5x_setup_dev2_win(u32 base, u32 size); +void orion5x_setup_pcie_wa_win(u32 base, u32 size); +void orion5x_setup_eth_wins(void); + +/* + * Shared code used internally by other Orion core functions. + * (/mach-orion/pci.c) + */ + +struct pci_sys_data; +struct pci_bus; + +void orion5x_pcie_id(u32 *dev, u32 *rev); +int orion5x_pcie_local_bus_nr(void); +int orion5x_pci_local_bus_nr(void); +int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); +struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); + +/* + * Valid GPIO pins according to MPP setup, used by machine-setup. + * (/mach-orion/gpio.c). + */ + +void orion5x_gpio_set_valid_pins(u32 pins); +void gpio_display(void); /* debug */ + +/* + * Pull in Orion Ethernet platform_data, used by machine-setup + */ + +struct mv643xx_eth_platform_data; + +void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); + +/* + * Orion Sata platform_data, used by machine-setup + */ + +struct mv_sata_platform_data; + +void orion5x_sata_init(struct mv_sata_platform_data *sata_data); + +struct machine_desc; +struct meminfo; +struct tag; +extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, + char **, struct meminfo *); + + +#endif diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c similarity index 90% rename from arch/arm/mach-orion/db88f5281-setup.c rename to arch/arm/mach-orion5x/db88f5281-setup.c index a0a9e4851b..872aed3723 100644 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/db88f5281-setup.c + * arch/arm/mach-orion5x/db88f5281-setup.c * * Marvell Orion-2 Development Board Setup * @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include "common.h" @@ -244,8 +244,8 @@ static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCIE IRQ is connected internally (not GPIO) */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; /* * PCI IRQs are connected via GPIOs @@ -265,8 +265,8 @@ static struct hw_pci db88f5281_pci __initdata = { .nr_controllers = 2, .preinit = db88f5281_pci_preinit, .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, .map_irq = db88f5281_pci_map_irq, }; @@ -312,16 +312,16 @@ static void __init db88f5281_init(void) /* * Basic Orion setup. Need to be called early. */ - orion_init(); + orion5x_init(); /* * Setup the CPU address decode windows for our on-board devices */ - orion_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, + orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, DB88F5281_NOR_BOOT_SIZE); - orion_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); - orion_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); - orion_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); + orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); + orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); + orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); /* * Setup Multiplexing Pins: @@ -337,25 +337,25 @@ static void __init db88f5281_init(void) * MPP18: UART1_CTS MPP19: UART1_RTS * MPP-DEV: DEV_D[16:31] */ - orion_write(MPP_0_7_CTRL, 0x00222203); - orion_write(MPP_8_15_CTRL, 0x44000000); - orion_write(MPP_16_19_CTRL, 0); - orion_write(MPP_DEV_CTRL, 0); + orion5x_write(MPP_0_7_CTRL, 0x00222203); + orion5x_write(MPP_8_15_CTRL, 0x44000000); + orion5x_write(MPP_16_19_CTRL, 0); + orion5x_write(MPP_DEV_CTRL, 0); - orion_gpio_set_valid_pins(0x00003fc3); + orion5x_gpio_set_valid_pins(0x00003fc3); platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); - orion_eth_init(&db88f5281_eth_data); + orion5x_eth_init(&db88f5281_eth_data); } MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") /* Maintainer: Tzachi Perelstein */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc, + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc, .boot_params = 0x00000100, .init_machine = db88f5281_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, MACHINE_END diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c similarity index 90% rename from arch/arm/mach-orion/dns323-setup.c rename to arch/arm/mach-orion5x/dns323-setup.c index 88991f7647..d67790ef23 100644 --- a/arch/arm/mach-orion/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/dns323-setup.c + * arch/arm/mach-orion5x/dns323-setup.c * * Copyright (C) 2007 Herbert Valerio Riedel * @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include "common.h" #define DNS323_GPIO_LED_RIGHT_AMBER 1 @@ -44,8 +44,8 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { /* PCI-E */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; pr_err("%s: requested mapping for unknown bus\n", __func__); @@ -55,8 +55,8 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci dns323_pci __initdata = { .nr_controllers = 1, .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, .map_irq = dns323_pci_map_irq, }; @@ -246,24 +246,25 @@ static void dns323_power_off(void) static void __init dns323_init(void) { /* Setup basic Orion functions. Need to be called early. */ - orion_init(); + orion5x_init(); /* setup flash mapping * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 */ - orion_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); + orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE * * Open a special address decode windows for the PCIE WA. */ - orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ - orion_write(MPP_0_7_CTRL, 0); - orion_write(MPP_8_15_CTRL, 0); - orion_write(MPP_16_19_CTRL, 0); - orion_write(MPP_DEV_CTRL, 0); + orion5x_write(MPP_0_7_CTRL, 0); + orion5x_write(MPP_8_15_CTRL, 0); + orion5x_write(MPP_16_19_CTRL, 0); + orion5x_write(MPP_DEV_CTRL, 0); /* Define used GPIO pins @@ -286,7 +287,7 @@ static void __init dns323_init(void) | 14 | Out | //unknown// | 15 | Out | //unknown// */ - orion_gpio_set_valid_pins(0x07f6); + orion5x_gpio_set_valid_pins(0x07f6); /* register dns323 specific power-off method */ if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) @@ -302,18 +303,18 @@ static void __init dns323_init(void) i2c_register_board_info(0, dns323_i2c_devices, ARRAY_SIZE(dns323_i2c_devices)); - orion_eth_init(&dns323_eth_data); + orion5x_eth_init(&dns323_eth_data); } /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ MACHINE_START(DNS323, "D-Link DNS-323") /* Maintainer: Herbert Valerio Riedel */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, .init_machine = dns323_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, .fixup = tag_fixup_mem32, MACHINE_END diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion5x/gpio.c similarity index 71% rename from arch/arm/mach-orion/gpio.c rename to arch/arm/mach-orion5x/gpio.c index afc7be08b3..8108c316c4 100644 --- a/arch/arm/mach-orion/gpio.c +++ b/arch/arm/mach-orion5x/gpio.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/gpio.c + * arch/arm/mach-orion5x/gpio.c * * GPIO functions for Marvell Orion System On Chip * @@ -17,14 +17,14 @@ #include #include #include -#include +#include #include "common.h" static DEFINE_SPINLOCK(gpio_lock); static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ -void __init orion_gpio_set_valid_pins(u32 pins) +void __init orion5x_gpio_set_valid_pins(u32 pins) { gpio_valid[0] = pins; } @@ -50,7 +50,7 @@ int gpio_direction_input(unsigned pin) if (!gpio_label[pin]) gpio_label[pin] = "?"; - orion_setbits(GPIO_IO_CONF, 1 << pin); + orion5x_setbits(GPIO_IO_CONF, 1 << pin); spin_unlock_irqrestore(&gpio_lock, flags); return 0; @@ -77,12 +77,12 @@ int gpio_direction_output(unsigned pin, int value) gpio_label[pin] = "?"; mask = 1 << pin; - orion_clrbits(GPIO_BLINK_EN, mask); + orion5x_clrbits(GPIO_BLINK_EN, mask); if (value) - orion_setbits(GPIO_OUT, mask); + orion5x_setbits(GPIO_OUT, mask); else - orion_clrbits(GPIO_OUT, mask); - orion_clrbits(GPIO_IO_CONF, mask); + orion5x_clrbits(GPIO_OUT, mask); + orion5x_clrbits(GPIO_IO_CONF, mask); spin_unlock_irqrestore(&gpio_lock, flags); return 0; @@ -93,10 +93,10 @@ int gpio_get_value(unsigned pin) { int val, mask = 1 << pin; - if (orion_read(GPIO_IO_CONF) & mask) - val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL); + if (orion5x_read(GPIO_IO_CONF) & mask) + val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL); else - val = orion_read(GPIO_OUT); + val = orion5x_read(GPIO_OUT); return val & mask; } @@ -109,32 +109,32 @@ void gpio_set_value(unsigned pin, int value) spin_lock_irqsave(&gpio_lock, flags); - orion_clrbits(GPIO_BLINK_EN, mask); + orion5x_clrbits(GPIO_BLINK_EN, mask); if (value) - orion_setbits(GPIO_OUT, mask); + orion5x_setbits(GPIO_OUT, mask); else - orion_clrbits(GPIO_OUT, mask); + orion5x_clrbits(GPIO_OUT, mask); spin_unlock_irqrestore(&gpio_lock, flags); } EXPORT_SYMBOL(gpio_set_value); -void orion_gpio_set_blink(unsigned pin, int blink) +void orion5x_gpio_set_blink(unsigned pin, int blink) { unsigned long flags; int mask = 1 << pin; spin_lock_irqsave(&gpio_lock, flags); - orion_clrbits(GPIO_OUT, mask); + orion5x_clrbits(GPIO_OUT, mask); if (blink) - orion_setbits(GPIO_BLINK_EN, mask); + orion5x_setbits(GPIO_BLINK_EN, mask); else - orion_clrbits(GPIO_BLINK_EN, mask); + orion5x_clrbits(GPIO_BLINK_EN, mask); spin_unlock_irqrestore(&gpio_lock, flags); } -EXPORT_SYMBOL(orion_gpio_set_blink); +EXPORT_SYMBOL(orion5x_gpio_set_blink); int gpio_request(unsigned pin, const char *label) { @@ -188,39 +188,39 @@ void gpio_display(void) printk("GPIO, free\n"); } else { printk("GPIO, used by %s, ", gpio_label[i]); - if (orion_read(GPIO_IO_CONF) & (1 << i)) { + if (orion5x_read(GPIO_IO_CONF) & (1 << i)) { printk("input, active %s, level %s, edge %s\n", - ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", - ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", - ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); + ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", + ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", + ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); } else { - printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1); + printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1); } } } printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", - MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL)); + MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL)); printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", - MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL)); + MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL)); printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", - MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL)); + MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL)); printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", - MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL)); + MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL)); printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", - GPIO_OUT, orion_read(GPIO_OUT)); + GPIO_OUT, orion5x_read(GPIO_OUT)); printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", - GPIO_IO_CONF, orion_read(GPIO_IO_CONF)); + GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF)); printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", - GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN)); + GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN)); printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", - GPIO_IN_POL, orion_read(GPIO_IN_POL)); + GPIO_IN_POL, orion5x_read(GPIO_IN_POL)); printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", - GPIO_DATA_IN, orion_read(GPIO_DATA_IN)); + GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN)); printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", - GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK)); + GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK)); printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", - GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE)); + GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE)); printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", - GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK)); + GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK)); } diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion5x/irq.c similarity index 62% rename from arch/arm/mach-orion/irq.c rename to arch/arm/mach-orion5x/irq.c index 7033cc1360..dd21f38c5d 100644 --- a/arch/arm/mach-orion/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/irq.c + * arch/arm/mach-orion5x/irq.c * * Core IRQ functions for Marvell Orion System On Chip * @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include "common.h" @@ -44,46 +44,46 @@ * polarity LEVEL mask * ****************************************************************************/ -static void orion_gpio_irq_ack(u32 irq) +static void orion5x_gpio_irq_ack(u32 irq) { int pin = irq_to_gpio(irq); if (irq_desc[irq].status & IRQ_LEVEL) /* * Mask bit for level interrupt */ - orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); + orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); else /* * Clear casue bit for egde interrupt */ - orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin); + orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin); } -static void orion_gpio_irq_mask(u32 irq) +static void orion5x_gpio_irq_mask(u32 irq) { int pin = irq_to_gpio(irq); if (irq_desc[irq].status & IRQ_LEVEL) - orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); + orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); else - orion_clrbits(GPIO_EDGE_MASK, 1 << pin); + orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin); } -static void orion_gpio_irq_unmask(u32 irq) +static void orion5x_gpio_irq_unmask(u32 irq) { int pin = irq_to_gpio(irq); if (irq_desc[irq].status & IRQ_LEVEL) - orion_setbits(GPIO_LEVEL_MASK, 1 << pin); + orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin); else - orion_setbits(GPIO_EDGE_MASK, 1 << pin); + orion5x_setbits(GPIO_EDGE_MASK, 1 << pin); } -static int orion_gpio_set_irq_type(u32 irq, u32 type) +static int orion5x_gpio_set_irq_type(u32 irq, u32 type) { int pin = irq_to_gpio(irq); struct irq_desc *desc; - if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) { - printk(KERN_ERR "orion_gpio_set_irq_type failed " + if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) { + printk(KERN_ERR "orion5x_gpio_set_irq_type failed " "(irq %d, pin %d).\n", irq, pin); return -EINVAL; } @@ -94,22 +94,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) case IRQT_HIGH: desc->handle_irq = handle_level_irq; desc->status |= IRQ_LEVEL; - orion_clrbits(GPIO_IN_POL, (1 << pin)); + orion5x_clrbits(GPIO_IN_POL, (1 << pin)); break; case IRQT_LOW: desc->handle_irq = handle_level_irq; desc->status |= IRQ_LEVEL; - orion_setbits(GPIO_IN_POL, (1 << pin)); + orion5x_setbits(GPIO_IN_POL, (1 << pin)); break; case IRQT_RISING: desc->handle_irq = handle_edge_irq; desc->status &= ~IRQ_LEVEL; - orion_clrbits(GPIO_IN_POL, (1 << pin)); + orion5x_clrbits(GPIO_IN_POL, (1 << pin)); break; case IRQT_FALLING: desc->handle_irq = handle_edge_irq; desc->status &= ~IRQ_LEVEL; - orion_setbits(GPIO_IN_POL, (1 << pin)); + orion5x_setbits(GPIO_IN_POL, (1 << pin)); break; case IRQT_BOTHEDGE: desc->handle_irq = handle_edge_irq; @@ -117,11 +117,11 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) /* * set initial polarity based on current input level */ - if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN)) + if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN)) & (1 << pin)) - orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ + orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ else - orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ + orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ break; default: @@ -135,22 +135,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) return 0; } -static struct irq_chip orion_gpio_irq_chip = { +static struct irq_chip orion5x_gpio_irq_chip = { .name = "Orion-IRQ-GPIO", - .ack = orion_gpio_irq_ack, - .mask = orion_gpio_irq_mask, - .unmask = orion_gpio_irq_unmask, - .set_type = orion_gpio_set_irq_type, + .ack = orion5x_gpio_irq_ack, + .mask = orion5x_gpio_irq_mask, + .unmask = orion5x_gpio_irq_unmask, + .set_type = orion5x_gpio_set_irq_type, }; -static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { u32 cause, offs, pin; - BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31); - offs = (irq - IRQ_ORION_GPIO_0_7) * 8; - cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) | - (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK)); + BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); + offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; + cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) | + (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK)); for (pin = offs; pin < offs + 8; pin++) { if (cause & (1 << pin)) { @@ -158,16 +158,16 @@ static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) desc = irq_desc + irq; if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { /* Swap polarity (race with GPIO line) */ - u32 polarity = orion_read(GPIO_IN_POL); + u32 polarity = orion5x_read(GPIO_IN_POL); polarity ^= 1 << pin; - orion_write(GPIO_IN_POL, polarity); + orion5x_write(GPIO_IN_POL, polarity); } desc_handle_irq(irq, desc); } } } -static void __init orion_init_gpio_irq(void) +static void __init orion5x_init_gpio_irq(void) { int i; struct irq_desc *desc; @@ -175,37 +175,37 @@ static void __init orion_init_gpio_irq(void) /* * Mask and clear GPIO IRQ interrupts */ - orion_write(GPIO_LEVEL_MASK, 0x0); - orion_write(GPIO_EDGE_MASK, 0x0); - orion_write(GPIO_EDGE_CAUSE, 0x0); + orion5x_write(GPIO_LEVEL_MASK, 0x0); + orion5x_write(GPIO_EDGE_MASK, 0x0); + orion5x_write(GPIO_EDGE_CAUSE, 0x0); /* * Register chained level handlers for GPIO IRQs by default. * User can use set_type() if he wants to use edge types handlers. */ - for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) { - set_irq_chip(i, &orion_gpio_irq_chip); + for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { + set_irq_chip(i, &orion5x_gpio_irq_chip); set_irq_handler(i, handle_level_irq); desc = irq_desc + i; desc->status |= IRQ_LEVEL; set_irq_flags(i, IRQF_VALID); } - set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler); } /***************************************************************************** * Orion Main IRQ ****************************************************************************/ -static void __init orion_init_main_irq(void) +static void __init orion5x_init_main_irq(void) { orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); } -void __init orion_init_irq(void) +void __init orion5x_init_irq(void) { - orion_init_main_irq(); - orion_init_gpio_irq(); + orion5x_init_main_irq(); + orion5x_init_gpio_irq(); } diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c similarity index 86% rename from arch/arm/mach-orion/kurobox_pro-setup.c rename to arch/arm/mach-orion5x/kurobox_pro-setup.c index be417e7f42..8ad4390b4b 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/kurobox_pro-setup.c + * arch/arm/mach-orion5x/kurobox_pro-setup.c * * Maintainer: Ronen Shitrit * @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include "common.h" @@ -123,8 +123,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCI isn't used on the Kuro */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; else printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); @@ -134,8 +134,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci kurobox_pro_pci __initdata = { .nr_controllers = 1, .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, .map_irq = kurobox_pro_pci_map_irq, }; @@ -188,19 +188,20 @@ static void __init kurobox_pro_init(void) /* * Setup basic Orion functions. Need to be called early. */ - orion_init(); + orion5x_init(); /* * Setup the CPU address decode windows for our devices */ - orion_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, + orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, KUROBOX_PRO_NOR_BOOT_SIZE); - orion_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); + orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); /* * Open a special address decode windows for the PCIE WA. */ - orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); /* * Setup Multiplexing Pins -- @@ -217,26 +218,26 @@ static void __init kurobox_pro_init(void) * MPP[15] SATA 1 active indication * MPP[16-19] Not used */ - orion_write(MPP_0_7_CTRL, 0x44220003); - orion_write(MPP_8_15_CTRL, 0x55550000); - orion_write(MPP_16_19_CTRL, 0x0); + orion5x_write(MPP_0_7_CTRL, 0x44220003); + orion5x_write(MPP_8_15_CTRL, 0x55550000); + orion5x_write(MPP_16_19_CTRL, 0x0); - orion_gpio_set_valid_pins(0x0000000c); + orion5x_gpio_set_valid_pins(0x0000000c); platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices)); i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); - orion_eth_init(&kurobox_pro_eth_data); - orion_sata_init(&kurobox_pro_sata_data); + orion5x_eth_init(&kurobox_pro_eth_data); + orion5x_sata_init(&kurobox_pro_sata_data); } MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") /* Maintainer: Ronen Shitrit */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, .init_machine = kurobox_pro_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, .fixup = tag_fixup_mem32, MACHINE_END diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion5x/pci.c similarity index 71% rename from arch/arm/mach-orion/pci.c rename to arch/arm/mach-orion5x/pci.c index 59684cc329..27b4afc8f4 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/pci.c + * arch/arm/mach-orion5x/pci.c * * PCI and PCIe functions for Marvell Orion System On Chip * @@ -33,15 +33,15 @@ /***************************************************************************** * PCIe controller ****************************************************************************/ -#define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE) +#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) -void __init orion_pcie_id(u32 *dev, u32 *rev) +void __init orion5x_pcie_id(u32 *dev, u32 *rev) { *dev = orion_pcie_dev_id(PCIE_BASE); *rev = orion_pcie_rev(PCIE_BASE); } -int orion_pcie_local_bus_nr(void) +int orion5x_pcie_local_bus_nr(void) { return orion_pcie_get_local_bus_nr(PCIE_BASE); } @@ -71,7 +71,7 @@ static int pcie_valid_config(int bus, int dev) * and then reading the PCIE_CONF_DATA register. Need to make sure these * transactions are atomic. */ -static DEFINE_SPINLOCK(orion_pcie_lock); +static DEFINE_SPINLOCK(orion5x_pcie_lock); static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) @@ -84,9 +84,9 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, return PCIBIOS_DEVICE_NOT_FOUND; } - spin_lock_irqsave(&orion_pcie_lock, flags); + spin_lock_irqsave(&orion5x_pcie_lock, flags); ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); - spin_unlock_irqrestore(&orion_pcie_lock, flags); + spin_unlock_irqrestore(&orion5x_pcie_lock, flags); return ret; } @@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, return PCIBIOS_DEVICE_NOT_FOUND; } - ret = orion_pcie_rd_conf_wa((void __iomem *)ORION_PCIE_WA_VIRT_BASE, + ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, bus, devfn, where, size, val); return ret; @@ -126,9 +126,9 @@ static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) return PCIBIOS_DEVICE_NOT_FOUND; - spin_lock_irqsave(&orion_pcie_lock, flags); + spin_lock_irqsave(&orion5x_pcie_lock, flags); ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); - spin_unlock_irqrestore(&orion_pcie_lock, flags); + spin_unlock_irqrestore(&orion5x_pcie_lock, flags); return ret; } @@ -147,7 +147,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) /* * Generic PCIe unit setup. */ - orion_pcie_setup(PCIE_BASE, &orion_mbus_dram_info); + orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); /* * Check whether to apply Orion-1/Orion-NAS PCIe config @@ -172,8 +172,8 @@ static int __init pcie_setup(struct pci_sys_data *sys) */ res[0].name = "PCIe I/O Space"; res[0].flags = IORESOURCE_IO; - res[0].start = ORION_PCIE_IO_BUS_BASE; - res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; + res[0].start = ORION5X_PCIE_IO_BUS_BASE; + res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; if (request_resource(&ioport_resource, &res[0])) panic("Request PCIe IO resource failed\n"); sys->resource[0] = &res[0]; @@ -183,8 +183,8 @@ static int __init pcie_setup(struct pci_sys_data *sys) */ res[1].name = "PCIe Memory Space"; res[1].flags = IORESOURCE_MEM; - res[1].start = ORION_PCIE_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; + res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; + res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; if (request_resource(&iomem_resource, &res[1])) panic("Request PCIe Memory resource failed\n"); sys->resource[1] = &res[1]; @@ -198,11 +198,11 @@ static int __init pcie_setup(struct pci_sys_data *sys) /***************************************************************************** * PCI controller ****************************************************************************/ -#define PCI_MODE ORION_PCI_REG(0xd00) -#define PCI_CMD ORION_PCI_REG(0xc00) -#define PCI_P2P_CONF ORION_PCI_REG(0x1d14) -#define PCI_CONF_ADDR ORION_PCI_REG(0xc78) -#define PCI_CONF_DATA ORION_PCI_REG(0xc7c) +#define PCI_MODE ORION5X_PCI_REG(0xd00) +#define PCI_CMD ORION5X_PCI_REG(0xc00) +#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) +#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) +#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) /* * PCI_MODE bits @@ -244,16 +244,16 @@ static int __init pcie_setup(struct pci_sys_data *sys) /* * PCI Address Decode Windows registers */ -#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ - ((n) == 1) ? ORION_PCI_REG(0xd08) : \ - ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ - ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) -#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ - ((n) == 1) ? ORION_PCI_REG(0xd48) : \ - ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ - ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) -#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) -#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) +#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ + ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ + ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ + ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) +#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) : \ + ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ + ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ + ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) +#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) +#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) /* * PCI configuration helpers for BAR settings @@ -267,45 +267,45 @@ static int __init pcie_setup(struct pci_sys_data *sys) * and then reading the PCI_CONF_DATA register. Need to make sure these * transactions are atomic. */ -static DEFINE_SPINLOCK(orion_pci_lock); +static DEFINE_SPINLOCK(orion5x_pci_lock); -int orion_pci_local_bus_nr(void) +int orion5x_pci_local_bus_nr(void) { - u32 conf = orion_read(PCI_P2P_CONF); + u32 conf = orion5x_read(PCI_P2P_CONF); return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); } -static int orion_pci_hw_rd_conf(int bus, int dev, u32 func, +static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, u32 where, u32 size, u32 *val) { unsigned long flags; - spin_lock_irqsave(&orion_pci_lock, flags); + spin_lock_irqsave(&orion5x_pci_lock, flags); - orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | + orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); - *val = orion_read(PCI_CONF_DATA); + *val = orion5x_read(PCI_CONF_DATA); if (size == 1) *val = (*val >> (8*(where & 0x3))) & 0xff; else if (size == 2) *val = (*val >> (8*(where & 0x3))) & 0xffff; - spin_unlock_irqrestore(&orion_pci_lock, flags); + spin_unlock_irqrestore(&orion5x_pci_lock, flags); return PCIBIOS_SUCCESSFUL; } -static int orion_pci_hw_wr_conf(int bus, int dev, u32 func, +static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, u32 where, u32 size, u32 val) { unsigned long flags; int ret = PCIBIOS_SUCCESSFUL; - spin_lock_irqsave(&orion_pci_lock, flags); + spin_lock_irqsave(&orion5x_pci_lock, flags); - orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | + orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); @@ -319,82 +319,82 @@ static int orion_pci_hw_wr_conf(int bus, int dev, u32 func, ret = PCIBIOS_BAD_REGISTER_NUMBER; } - spin_unlock_irqrestore(&orion_pci_lock, flags); + spin_unlock_irqrestore(&orion5x_pci_lock, flags); return ret; } -static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, +static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { /* * Don't go out for local device */ - if (bus->number == orion_pci_local_bus_nr() && + if (bus->number == orion5x_pci_local_bus_nr() && PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; } - return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), + return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); } -static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, +static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - if (bus->number == orion_pci_local_bus_nr() && + if (bus->number == orion5x_pci_local_bus_nr() && PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) return PCIBIOS_DEVICE_NOT_FOUND; - return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), + return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); } static struct pci_ops pci_ops = { - .read = orion_pci_rd_conf, - .write = orion_pci_wr_conf, + .read = orion5x_pci_rd_conf, + .write = orion5x_pci_wr_conf, }; -static void __init orion_pci_set_bus_nr(int nr) +static void __init orion5x_pci_set_bus_nr(int nr) { - u32 p2p = orion_read(PCI_P2P_CONF); + u32 p2p = orion5x_read(PCI_P2P_CONF); - if (orion_read(PCI_MODE) & PCI_MODE_PCIX) { + if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) { /* * PCI-X mode */ u32 pcix_status, bus, dev; bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; - orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); + orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); pcix_status &= ~PCIX_STAT_BUS_MASK; pcix_status |= (nr << PCIX_STAT_BUS_OFFS); - orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); + orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); } else { /* * PCI Conventional mode */ p2p &= ~PCI_P2P_BUS_MASK; p2p |= (nr << PCI_P2P_BUS_OFFS); - orion_write(PCI_P2P_CONF, p2p); + orion5x_write(PCI_P2P_CONF, p2p); } } -static void __init orion_pci_master_slave_enable(void) +static void __init orion5x_pci_master_slave_enable(void) { int bus_nr, func, reg; u32 val; - bus_nr = orion_pci_local_bus_nr(); + bus_nr = orion5x_pci_local_bus_nr(); func = PCI_CONF_FUNC_STAT_CMD; reg = PCI_CONF_REG_STAT_CMD; - orion_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); + orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - orion_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); + orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); } -static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) +static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) { u32 win_enable; int bus; @@ -404,12 +404,12 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) * First, disable windows. */ win_enable = 0xffffffff; - orion_write(PCI_BAR_ENABLE, win_enable); + orion5x_write(PCI_BAR_ENABLE, win_enable); /* * Setup windows for DDR banks. */ - bus = orion_pci_local_bus_nr(); + bus = orion5x_pci_local_bus_nr(); for (i = 0; i < dram->num_cs; i++) { struct mbus_dram_window *cs = dram->cs + i; @@ -421,18 +421,18 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) * Write DRAM bank base address register. */ reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); - orion_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); + orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); val = (cs->base & 0xfffff000) | (val & 0xfff); - orion_pci_hw_wr_conf(bus, 0, func, reg, 4, val); + orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); /* * Write DRAM bank size register. */ reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); - orion_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); - orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), + orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); + orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), (cs->size - 1) & 0xfffff000); - orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), + orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), cs->base & 0xfffff000); /* @@ -444,12 +444,12 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) /* * Re-enable decode windows. */ - orion_write(PCI_BAR_ENABLE, win_enable); + orion5x_write(PCI_BAR_ENABLE, win_enable); /* * Disable automatic update of address remaping when writing to BARs. */ - orion_setbits(PCI_ADDR_DECODE_CTRL, 1); + orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); } static int __init pci_setup(struct pci_sys_data *sys) @@ -459,17 +459,17 @@ static int __init pci_setup(struct pci_sys_data *sys) /* * Point PCI unit MBUS decode windows to DRAM space. */ - orion_setup_pci_wins(&orion_mbus_dram_info); + orion5x_setup_pci_wins(&orion5x_mbus_dram_info); /* * Master + Slave enable */ - orion_pci_master_slave_enable(); + orion5x_pci_master_slave_enable(); /* * Force ordering */ - orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); + orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); /* * Request resources @@ -483,8 +483,8 @@ static int __init pci_setup(struct pci_sys_data *sys) */ res[0].name = "PCI I/O Space"; res[0].flags = IORESOURCE_IO; - res[0].start = ORION_PCI_IO_BUS_BASE; - res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; + res[0].start = ORION5X_PCI_IO_BUS_BASE; + res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; if (request_resource(&ioport_resource, &res[0])) panic("Request PCI IO resource failed\n"); sys->resource[0] = &res[0]; @@ -494,8 +494,8 @@ static int __init pci_setup(struct pci_sys_data *sys) */ res[1].name = "PCI Memory Space"; res[1].flags = IORESOURCE_MEM; - res[1].start = ORION_PCI_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; + res[1].start = ORION5X_PCI_MEM_PHYS_BASE; + res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; if (request_resource(&iomem_resource, &res[1])) panic("Request PCI Memory resource failed\n"); sys->resource[1] = &res[1]; @@ -527,7 +527,7 @@ static void __devinit rc_pci_fixup(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); -int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys) +int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) { int ret = 0; @@ -535,14 +535,14 @@ int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys) orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); ret = pcie_setup(sys); } else if (nr == 1) { - orion_pci_set_bus_nr(sys->busnr); + orion5x_pci_set_bus_nr(sys->busnr); ret = pci_setup(sys); } return ret; } -struct pci_bus __init *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) +struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) { struct pci_bus *bus; diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c similarity index 89% rename from arch/arm/mach-orion/rd88f5182-setup.c rename to arch/arm/mach-orion5x/rd88f5182-setup.c index f3e38ecda1..37e8b2dc3e 100644 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/rd88f5182-setup.c + * arch/arm/mach-orion5x/rd88f5182-setup.c * * Marvell Orion-NAS Reference Design Setup * @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include "common.h" /***************************************************************************** @@ -175,8 +175,8 @@ static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCI-E isn't used on the RD2 */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; /* * PCI IRQs are connected via GPIOs @@ -196,8 +196,8 @@ static struct hw_pci rd88f5182_pci __initdata = { .nr_controllers = 2, .preinit = rd88f5182_pci_preinit, .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, .map_irq = rd88f5182_pci_map_irq, }; @@ -249,19 +249,20 @@ static void __init rd88f5182_init(void) /* * Setup basic Orion functions. Need to be called early. */ - orion_init(); + orion5x_init(); /* * Setup the CPU address decode windows for our devices */ - orion_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, + orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, RD88F5182_NOR_BOOT_SIZE); - orion_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); + orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); /* * Open a special address decode windows for the PCIE WA. */ - orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); /* * Setup Multiplexing Pins -- @@ -287,25 +288,25 @@ static void __init rd88f5182_init(void) * MPP[25] USB 0 over current enable */ - orion_write(MPP_0_7_CTRL, 0x00000003); - orion_write(MPP_8_15_CTRL, 0x55550000); - orion_write(MPP_16_19_CTRL, 0x5555); + orion5x_write(MPP_0_7_CTRL, 0x00000003); + orion5x_write(MPP_8_15_CTRL, 0x55550000); + orion5x_write(MPP_16_19_CTRL, 0x5555); - orion_gpio_set_valid_pins(0x000000fb); + orion5x_gpio_set_valid_pins(0x000000fb); platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); - orion_eth_init(&rd88f5182_eth_data); - orion_sata_init(&rd88f5182_sata_data); + orion5x_eth_init(&rd88f5182_eth_data); + orion5x_sata_init(&rd88f5182_sata_data); } MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") /* Maintainer: Ronen Shitrit */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, .init_machine = rd88f5182_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, MACHINE_END diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c similarity index 88% rename from arch/arm/mach-orion/ts209-setup.c rename to arch/arm/mach-orion5x/ts209-setup.c index 8eca070006..71b0cffa2f 100644 --- a/arch/arm/mach-orion/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include "common.h" #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 @@ -144,8 +144,8 @@ static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCIE IRQ is connected internally (not GPIO) */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; /* * PCI IRQs are connected via GPIOs @@ -164,8 +164,8 @@ static struct hw_pci qnap_ts209_pci __initdata = { .nr_controllers = 2, .preinit = qnap_ts209_pci_preinit, .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, .map_irq = qnap_ts209_pci_map_irq, }; @@ -261,21 +261,21 @@ static struct platform_device *qnap_ts209_devices[] __initdata = { static void qnap_ts209_power_off(void) { /* 19200 baud divisor */ - const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200)); + const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200)); pr_info("%s: triggering power-off...\n", __func__); /* hijack uart1 and reset into sane state (19200,8n1) */ - orion_write(UART1_REG(LCR), 0x83); - orion_write(UART1_REG(DLL), divisor & 0xff); - orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff); - orion_write(UART1_REG(LCR), 0x03); - orion_write(UART1_REG(IER), 0x00); - orion_write(UART1_REG(FCR), 0x00); - orion_write(UART1_REG(MCR), 0x00); + orion5x_write(UART1_REG(LCR), 0x83); + orion5x_write(UART1_REG(DLL), divisor & 0xff); + orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff); + orion5x_write(UART1_REG(LCR), 0x03); + orion5x_write(UART1_REG(IER), 0x00); + orion5x_write(UART1_REG(FCR), 0x00); + orion5x_write(UART1_REG(MCR), 0x00); /* send the power-off command 'A' to PIC */ - orion_write(UART1_REG(TX), 'A'); + orion5x_write(UART1_REG(TX), 'A'); } static void __init qnap_ts209_init(void) @@ -283,18 +283,19 @@ static void __init qnap_ts209_init(void) /* * Setup basic Orion functions. Need to be called early. */ - orion_init(); + orion5x_init(); /* * Setup flash mapping */ - orion_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, + orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, QNAP_TS209_NOR_BOOT_SIZE); /* * Open a special address decode windows for the PCIE WA. */ - orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); /* * Setup Multiplexing Pins -- @@ -319,10 +320,10 @@ static void __init qnap_ts209_init(void) * MPP[22] USB 0 over current * MPP[23-25] Reserved */ - orion_write(MPP_0_7_CTRL, 0x3); - orion_write(MPP_8_15_CTRL, 0x55550000); - orion_write(MPP_16_19_CTRL, 0x5500); - orion_gpio_set_valid_pins(0x3cc0fff); + orion5x_write(MPP_0_7_CTRL, 0x3); + orion5x_write(MPP_8_15_CTRL, 0x55550000); + orion5x_write(MPP_16_19_CTRL, 0x5500); + orion5x_gpio_set_valid_pins(0x3cc0fff); /* register ts209 specific power-off method */ pm_power_off = qnap_ts209_power_off; @@ -341,18 +342,18 @@ static void __init qnap_ts209_init(void) pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); - orion_eth_init(&qnap_ts209_eth_data); - orion_sata_init(&qnap_ts209_sata_data); + orion5x_eth_init(&qnap_ts209_eth_data); + orion5x_sata_init(&qnap_ts209_sata_data); } MACHINE_START(TS209, "QNAP TS-109/TS-209") /* Maintainer: Byron Bradley */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, .init_machine = qnap_ts209_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, .fixup = tag_fixup_mem32, MACHINE_END diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 76348f060f..64d09244df 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -345,7 +345,7 @@ config CPU_XSC3 # Feroceon config CPU_FEROCEON bool - depends on ARCH_ORION + depends on ARCH_ORION5X default y select CPU_32v5 select CPU_ABRT_EV5T diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h deleted file mode 100644 index 70a2420456..0000000000 --- a/include/asm-arm/arch-orion/irqs.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * include/asm-arm/arch-orion/irqs.h - * - * IRQ definitions for Orion SoC - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#include "orion.h" /* need GPIO_MAX */ - -/* - * Orion Main Interrupt Controller - */ -#define IRQ_ORION_BRIDGE 0 -#define IRQ_ORION_DOORBELL_H2C 1 -#define IRQ_ORION_DOORBELL_C2H 2 -#define IRQ_ORION_UART0 3 -#define IRQ_ORION_UART1 4 -#define IRQ_ORION_I2C 5 -#define IRQ_ORION_GPIO_0_7 6 -#define IRQ_ORION_GPIO_8_15 7 -#define IRQ_ORION_GPIO_16_23 8 -#define IRQ_ORION_GPIO_24_31 9 -#define IRQ_ORION_PCIE0_ERR 10 -#define IRQ_ORION_PCIE0_INT 11 -#define IRQ_ORION_USB1_CTRL 12 -#define IRQ_ORION_DEV_BUS_ERR 14 -#define IRQ_ORION_PCI_ERR 15 -#define IRQ_ORION_USB_BR_ERR 16 -#define IRQ_ORION_USB0_CTRL 17 -#define IRQ_ORION_ETH_RX 18 -#define IRQ_ORION_ETH_TX 19 -#define IRQ_ORION_ETH_MISC 20 -#define IRQ_ORION_ETH_SUM 21 -#define IRQ_ORION_ETH_ERR 22 -#define IRQ_ORION_IDMA_ERR 23 -#define IRQ_ORION_IDMA_0 24 -#define IRQ_ORION_IDMA_1 25 -#define IRQ_ORION_IDMA_2 26 -#define IRQ_ORION_IDMA_3 27 -#define IRQ_ORION_CESA 28 -#define IRQ_ORION_SATA 29 -#define IRQ_ORION_XOR0 30 -#define IRQ_ORION_XOR1 31 - -/* - * Orion General Purpose Pins - */ -#define IRQ_ORION_GPIO_START 32 -#define NR_GPIO_IRQS GPIO_MAX - -#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS) - - -#endif diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h deleted file mode 100644 index 01f1299472..0000000000 --- a/include/asm-arm/arch-orion/orion.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * include/asm-arm/arch-orion/orion.h - * - * Generic definitions of Orion SoC flavors: - * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_ORION_H -#define __ASM_ARCH_ORION_H - -/***************************************************************************** - * Orion Address Maps - * - * phys - * e0000000 PCIe MEM space - * e8000000 PCI MEM space - * f0000000 PCIe WA space (Orion-1/Orion-NAS only) - * f1000000 on-chip peripheral registers - * f2000000 PCIe I/O space - * f2100000 PCI I/O space - * f4000000 device bus mappings (boot) - * fa000000 device bus mappings (cs0) - * fa800000 device bus mappings (cs2) - * fc000000 device bus mappings (cs0/cs1) - * - * virt phys size - * fdd00000 f1000000 1M on-chip peripheral registers - * fde00000 f2000000 1M PCIe I/O space - * fdf00000 f2100000 1M PCI I/O space - * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) - ****************************************************************************/ -#define ORION_REGS_PHYS_BASE 0xf1000000 -#define ORION_REGS_VIRT_BASE 0xfdd00000 -#define ORION_REGS_SIZE SZ_1M - -#define ORION_PCIE_IO_PHYS_BASE 0xf2000000 -#define ORION_PCIE_IO_VIRT_BASE 0xfde00000 -#define ORION_PCIE_IO_BUS_BASE 0x00000000 -#define ORION_PCIE_IO_SIZE SZ_1M - -#define ORION_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION_PCI_IO_VIRT_BASE 0xfdf00000 -#define ORION_PCI_IO_BUS_BASE 0x00100000 -#define ORION_PCI_IO_SIZE SZ_1M - -/* Relevant only for Orion-1/Orion-NAS */ -#define ORION_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION_PCIE_WA_VIRT_BASE 0xfe000000 -#define ORION_PCIE_WA_SIZE SZ_16M - -#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000 -#define ORION_PCIE_MEM_SIZE SZ_128M - -#define ORION_PCI_MEM_PHYS_BASE 0xe8000000 -#define ORION_PCI_MEM_SIZE SZ_128M - -/******************************************************************************* - * Supported Devices & Revisions - ******************************************************************************/ -/* Orion-1 (88F5181) */ -#define MV88F5181_DEV_ID 0x5181 -#define MV88F5181_REV_B1 3 -/* Orion-NAS (88F5182) */ -#define MV88F5182_DEV_ID 0x5182 -#define MV88F5182_REV_A2 2 -/* Orion-2 (88F5281) */ -#define MV88F5281_DEV_ID 0x5281 -#define MV88F5281_REV_D1 5 -#define MV88F5281_REV_D2 6 - -/******************************************************************************* - * Orion Registers Map - ******************************************************************************/ -#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000) -#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x)) - -#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000) -#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000) -#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x)) -#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000) -#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100) - -#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000) -#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x)) -#define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300) - -#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000) -#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x)) - -#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000) -#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x)) - -#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000) -#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000) -#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x)) - -#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000) -#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000) -#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x)) - -#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000) -#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000) -#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x)) - -#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000) -#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000) -#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x)) - -/******************************************************************************* - * Device Bus Registers - ******************************************************************************/ -#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000) -#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004) -#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050) -#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008) -#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010) -#define GPIO_OUT ORION_DEV_BUS_REG(0x100) -#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104) -#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108) -#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c) -#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110) -#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114) -#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118) -#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c) -#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c) -#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460) -#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464) -#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c) -#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) -#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) -#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) -#define GPIO_MAX 32 - -/*************************************************************************** - * Orion CPU Bridge Registers - **************************************************************************/ -#define CPU_CONF ORION_BRIDGE_REG(0x100) -#define CPU_CTRL ORION_BRIDGE_REG(0x104) -#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108) -#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c) -#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C) -#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110) -#define BRIDGE_MASK ORION_BRIDGE_REG(0x114) -#define BRIDGE_INT_TIMER0 0x0002 -#define BRIDGE_INT_TIMER1 0x0004 -#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200) -#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204) - - -#endif diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion5x/debug-macro.S similarity index 73% rename from include/asm-arm/arch-orion/debug-macro.S rename to include/asm-arm/arch-orion5x/debug-macro.S index c847f8c925..4f98f3ba29 100644 --- a/include/asm-arm/arch-orion/debug-macro.S +++ b/include/asm-arm/arch-orion5x/debug-macro.S @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/debug-macro.S + * include/asm-arm/arch-orion5x/debug-macro.S * * Debugging macro include header * @@ -8,13 +8,13 @@ * published by the Free Software Foundation. */ -#include +#include .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - ldreq \rx, =ORION_REGS_PHYS_BASE - ldrne \rx, =ORION_REGS_VIRT_BASE + ldreq \rx, =ORION5X_REGS_PHYS_BASE + ldrne \rx, =ORION5X_REGS_VIRT_BASE orr \rx, \rx, #0x00012000 .endm diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion5x/dma.h similarity index 100% rename from include/asm-arm/arch-orion/dma.h rename to include/asm-arm/arch-orion5x/dma.h diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion5x/entry-macro.S similarity index 90% rename from include/asm-arm/arch-orion/entry-macro.S rename to include/asm-arm/arch-orion5x/entry-macro.S index cda096b2ac..d8ef54c0ee 100644 --- a/include/asm-arm/arch-orion/entry-macro.S +++ b/include/asm-arm/arch-orion5x/entry-macro.S @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/entry-macro.S + * include/asm-arm/arch-orion5x/entry-macro.S * * Low-level IRQ helper macros for Orion platforms * @@ -8,7 +8,7 @@ * warranty of any kind, whether express or implied. */ -#include +#include .macro disable_fiq .endm diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion5x/gpio.h similarity index 79% rename from include/asm-arm/arch-orion/gpio.h rename to include/asm-arm/arch-orion5x/gpio.h index d66284f9a1..c85e498388 100644 --- a/include/asm-arm/arch-orion/gpio.h +++ b/include/asm-arm/arch-orion5x/gpio.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/gpio.h + * include/asm-arm/arch-orion5x/gpio.h * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -12,17 +12,17 @@ extern int gpio_direction_input(unsigned pin); extern int gpio_direction_output(unsigned pin, int value); extern int gpio_get_value(unsigned pin); extern void gpio_set_value(unsigned pin, int value); -extern void orion_gpio_set_blink(unsigned pin, int blink); +extern void orion5x_gpio_set_blink(unsigned pin, int blink); extern void gpio_display(void); /* debug */ static inline int gpio_to_irq(int pin) { - return pin + IRQ_ORION_GPIO_START; + return pin + IRQ_ORION5X_GPIO_START; } static inline int irq_to_gpio(int irq) { - return irq - IRQ_ORION_GPIO_START; + return irq - IRQ_ORION5X_GPIO_START; } #include /* cansleep wrappers */ diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion5x/hardware.h similarity index 77% rename from include/asm-arm/arch-orion/hardware.h rename to include/asm-arm/arch-orion5x/hardware.h index 998af6029c..5d2d8e0b56 100644 --- a/include/asm-arm/arch-orion/hardware.h +++ b/include/asm-arm/arch-orion5x/hardware.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/hardware.h + * include/asm-arm/arch-orion5x/hardware.h * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -9,13 +9,13 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H -#include "orion.h" +#include "orion5x.h" #define pcibios_assign_all_busses() 1 #define PCIBIOS_MIN_IO 0x00001000 #define PCIBIOS_MIN_MEM 0x01000000 -#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE +#define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE #endif diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion5x/io.h similarity index 61% rename from include/asm-arm/arch-orion/io.h rename to include/asm-arm/arch-orion5x/io.h index 23820153b6..5148ab7ad1 100644 --- a/include/asm-arm/arch-orion/io.h +++ b/include/asm-arm/arch-orion5x/io.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/io.h + * include/asm-arm/arch-orion5x/io.h * * Tzachi Perelstein * @@ -11,20 +11,20 @@ #ifndef __ASM_ARCH_IO_H #define __ASM_ARCH_IO_H -#include "orion.h" +#include "orion5x.h" #define IO_SPACE_LIMIT 0xffffffff -#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE +#define IO_SPACE_REMAP ORION5X_PCI_SYS_IO_BASE static inline void __iomem * __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) { void __iomem *retval; - if (mtype == MT_DEVICE && size && paddr >= ORION_REGS_PHYS_BASE && - paddr + size <= ORION_REGS_PHYS_BASE + ORION_REGS_SIZE) { - retval = (void __iomem *)ORION_REGS_VIRT_BASE + - (paddr - ORION_REGS_PHYS_BASE); + if (mtype == MT_DEVICE && size && paddr >= ORION5X_REGS_PHYS_BASE && + paddr + size <= ORION5X_REGS_PHYS_BASE + ORION5X_REGS_SIZE) { + retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + + (paddr - ORION5X_REGS_PHYS_BASE); } else { retval = __arm_ioremap(paddr, size, mtype); } @@ -35,8 +35,8 @@ __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) static inline void __arch_iounmap(void __iomem *addr) { - if (addr < (void __iomem *)ORION_REGS_VIRT_BASE || - addr >= (void __iomem *)(ORION_REGS_VIRT_BASE + ORION_REGS_SIZE)) + if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE || + addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE)) __iounmap(addr); } @@ -54,15 +54,15 @@ static inline void __iomem *__io(unsigned long addr) /***************************************************************************** * Helpers to access Orion registers ****************************************************************************/ -#define orion_read(r) __raw_readl(r) -#define orion_write(r, val) __raw_writel(val, r) +#define orion5x_read(r) __raw_readl(r) +#define orion5x_write(r, val) __raw_writel(val, r) /* * These are not preempt-safe. Locks, if needed, must be taken * care of by the caller. */ -#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask)) -#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask)) +#define orion5x_setbits(r, mask) orion5x_write((r), orion5x_read(r) | (mask)) +#define orion5x_clrbits(r, mask) orion5x_write((r), orion5x_read(r) & ~(mask)) #endif diff --git a/include/asm-arm/arch-orion5x/irqs.h b/include/asm-arm/arch-orion5x/irqs.h new file mode 100644 index 0000000000..abdd61a483 --- /dev/null +++ b/include/asm-arm/arch-orion5x/irqs.h @@ -0,0 +1,62 @@ +/* + * include/asm-arm/arch-orion5x/irqs.h + * + * IRQ definitions for Orion SoC + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#include "orion5x.h" /* need GPIO_MAX */ + +/* + * Orion Main Interrupt Controller + */ +#define IRQ_ORION5X_BRIDGE 0 +#define IRQ_ORION5X_DOORBELL_H2C 1 +#define IRQ_ORION5X_DOORBELL_C2H 2 +#define IRQ_ORION5X_UART0 3 +#define IRQ_ORION5X_UART1 4 +#define IRQ_ORION5X_I2C 5 +#define IRQ_ORION5X_GPIO_0_7 6 +#define IRQ_ORION5X_GPIO_8_15 7 +#define IRQ_ORION5X_GPIO_16_23 8 +#define IRQ_ORION5X_GPIO_24_31 9 +#define IRQ_ORION5X_PCIE0_ERR 10 +#define IRQ_ORION5X_PCIE0_INT 11 +#define IRQ_ORION5X_USB1_CTRL 12 +#define IRQ_ORION5X_DEV_BUS_ERR 14 +#define IRQ_ORION5X_PCI_ERR 15 +#define IRQ_ORION5X_USB_BR_ERR 16 +#define IRQ_ORION5X_USB0_CTRL 17 +#define IRQ_ORION5X_ETH_RX 18 +#define IRQ_ORION5X_ETH_TX 19 +#define IRQ_ORION5X_ETH_MISC 20 +#define IRQ_ORION5X_ETH_SUM 21 +#define IRQ_ORION5X_ETH_ERR 22 +#define IRQ_ORION5X_IDMA_ERR 23 +#define IRQ_ORION5X_IDMA_0 24 +#define IRQ_ORION5X_IDMA_1 25 +#define IRQ_ORION5X_IDMA_2 26 +#define IRQ_ORION5X_IDMA_3 27 +#define IRQ_ORION5X_CESA 28 +#define IRQ_ORION5X_SATA 29 +#define IRQ_ORION5X_XOR0 30 +#define IRQ_ORION5X_XOR1 31 + +/* + * Orion General Purpose Pins + */ +#define IRQ_ORION5X_GPIO_START 32 +#define NR_GPIO_IRQS GPIO_MAX + +#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) + + +#endif diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion5x/memory.h similarity index 85% rename from include/asm-arm/arch-orion/memory.h rename to include/asm-arm/arch-orion5x/memory.h index d9300d62a5..80053a7afc 100644 --- a/include/asm-arm/arch-orion/memory.h +++ b/include/asm-arm/arch-orion5x/memory.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/memory.h + * include/asm-arm/arch-orion5x/memory.h * * Marvell Orion memory definitions */ diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h new file mode 100644 index 0000000000..206ddd71e1 --- /dev/null +++ b/include/asm-arm/arch-orion5x/orion5x.h @@ -0,0 +1,159 @@ +/* + * include/asm-arm/arch-orion5x/orion5x.h + * + * Generic definitions of Orion SoC flavors: + * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_ORION5X_H +#define __ASM_ARCH_ORION5X_H + +/***************************************************************************** + * Orion Address Maps + * + * phys + * e0000000 PCIe MEM space + * e8000000 PCI MEM space + * f0000000 PCIe WA space (Orion-1/Orion-NAS only) + * f1000000 on-chip peripheral registers + * f2000000 PCIe I/O space + * f2100000 PCI I/O space + * f4000000 device bus mappings (boot) + * fa000000 device bus mappings (cs0) + * fa800000 device bus mappings (cs2) + * fc000000 device bus mappings (cs0/cs1) + * + * virt phys size + * fdd00000 f1000000 1M on-chip peripheral registers + * fde00000 f2000000 1M PCIe I/O space + * fdf00000 f2100000 1M PCI I/O space + * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) + ****************************************************************************/ +#define ORION5X_REGS_PHYS_BASE 0xf1000000 +#define ORION5X_REGS_VIRT_BASE 0xfdd00000 +#define ORION5X_REGS_SIZE SZ_1M + +#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 +#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 +#define ORION5X_PCIE_IO_BUS_BASE 0x00000000 +#define ORION5X_PCIE_IO_SIZE SZ_1M + +#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 +#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 +#define ORION5X_PCI_IO_BUS_BASE 0x00100000 +#define ORION5X_PCI_IO_SIZE SZ_1M + +/* Relevant only for Orion-1/Orion-NAS */ +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 +#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 +#define ORION5X_PCIE_WA_SIZE SZ_16M + +#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 +#define ORION5X_PCIE_MEM_SIZE SZ_128M + +#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 +#define ORION5X_PCI_MEM_SIZE SZ_128M + +/******************************************************************************* + * Supported Devices & Revisions + ******************************************************************************/ +/* Orion-1 (88F5181) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 + +/******************************************************************************* + * Orion Registers Map + ******************************************************************************/ +#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) +#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) + +#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) +#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) +#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) +#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) +#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) +#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) +#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) +#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) + +#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) +#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) +#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) + +#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) +#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) + +#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) +#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x)) + +#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) +#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) +#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x)) + +#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) +#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) +#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x)) + +#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) +#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) +#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x)) + +#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) +#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) +#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x)) + +/******************************************************************************* + * Device Bus Registers + ******************************************************************************/ +#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) +#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) +#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) +#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) +#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) +#define GPIO_OUT ORION5X_DEV_BUS_REG(0x100) +#define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104) +#define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108) +#define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c) +#define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110) +#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114) +#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118) +#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c) +#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) +#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) +#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) +#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) +#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) +#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) +#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) +#define GPIO_MAX 32 + +/*************************************************************************** + * Orion CPU Bridge Registers + **************************************************************************/ +#define CPU_CONF ORION5X_BRIDGE_REG(0x100) +#define CPU_CTRL ORION5X_BRIDGE_REG(0x104) +#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) +#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) +#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) +#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) +#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) +#define BRIDGE_INT_TIMER0 0x0002 +#define BRIDGE_INT_TIMER1 0x0004 +#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) +#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) + + +#endif diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion5x/system.h similarity index 76% rename from include/asm-arm/arch-orion/system.h rename to include/asm-arm/arch-orion5x/system.h index 653f992bbe..3f1d1e2d38 100644 --- a/include/asm-arm/arch-orion/system.h +++ b/include/asm-arm/arch-orion5x/system.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/system.h + * include/asm-arm/arch-orion5x/system.h * * Tzachi Perelstein * @@ -12,7 +12,7 @@ #define __ASM_ARCH_SYSTEM_H #include -#include +#include static inline void arch_idle(void) { @@ -24,8 +24,8 @@ static inline void arch_reset(char mode) /* * Enable and issue soft reset */ - orion_setbits(CPU_RESET_MASK, (1 << 2)); - orion_setbits(CPU_SOFT_RESET, 1); + orion5x_setbits(CPU_RESET_MASK, (1 << 2)); + orion5x_setbits(CPU_SOFT_RESET, 1); } diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion5x/timex.h similarity index 79% rename from include/asm-arm/arch-orion/timex.h rename to include/asm-arm/arch-orion5x/timex.h index 85588d9c22..31c568e28c 100644 --- a/include/asm-arm/arch-orion/timex.h +++ b/include/asm-arm/arch-orion5x/timex.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/timex.h + * include/asm-arm/arch-orion5x/timex.h * * Tzachi Perelstein * @@ -10,4 +10,4 @@ #define CLOCK_TICK_RATE (100 * HZ) -#define ORION_TCLK 166666667 +#define ORION5X_TCLK 166666667 diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h similarity index 89% rename from include/asm-arm/arch-orion/uncompress.h rename to include/asm-arm/arch-orion5x/uncompress.h index 03306cdd51..5c13d4fafb 100644 --- a/include/asm-arm/arch-orion/uncompress.h +++ b/include/asm-arm/arch-orion5x/uncompress.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/uncompress.h + * include/asm-arm/arch-orion5x/uncompress.h * * Tzachi Perelstein * @@ -8,7 +8,7 @@ * warranty of any kind, whether express or implied. */ -#include +#include #define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) #define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion5x/vmalloc.h similarity index 51% rename from include/asm-arm/arch-orion/vmalloc.h rename to include/asm-arm/arch-orion5x/vmalloc.h index 9d580278d2..2b3061e90d 100644 --- a/include/asm-arm/arch-orion/vmalloc.h +++ b/include/asm-arm/arch-orion5x/vmalloc.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/vmalloc.h + * include/asm-arm/arch-orion5x/vmalloc.h */ #define VMALLOC_END 0xfd800000