From: Chris Dearman <chris@mips.com>
Date: Mon, 7 Aug 2006 14:08:01 +0000 (+0100)
Subject: [MIPS] MT: Initialise all writable bits in Cause register to zero.
X-Git-Tag: v2.6.19-rc1~1055
X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=847b9dfccad7dd34b2e44b1c6ceeb1c4cb88084a;p=linux-2.6

[MIPS] MT: Initialise all writable bits in Cause register to zero.

Recent 34Ks come out of reset with WP enabled on VPE 1 so we take an
immediate exception when starting the second VPE.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 93429a4d30..766253c44f 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -203,7 +203,7 @@ void plat_smp_setup(void)
 				write_vpe_c0_config( read_c0_config());
 
 				/* make sure there are no software interrupts pending */
-				write_vpe_c0_cause(read_vpe_c0_cause() & ~(C_SW1|C_SW0));
+				write_vpe_c0_cause(0);
 
 				/* Propagate Config7 */
 				write_vpe_c0_config7(read_c0_config7());