From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Date: Fri, 27 Jun 2008 21:52:26 +0000 (+0200)
Subject: [MIPS] IP22: Fix crashes due to wrong L1_CACHE_BYTES
X-Git-Tag: v2.6.26-rc9~64^2~1
X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7e3297dc280f88ec0c6619a895f3d449776f952e;p=linux-2.6

[MIPS] IP22: Fix crashes due to wrong L1_CACHE_BYTES

The introduction of a real dma cache invalidate makes it important
to have a correct cache line size, otherwise the kernel will gives
out two memory segment, which might share one cache line. The R4400
Indy/Indigo2 CPU modules are using a second level cache line size
of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for
IP22.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e5a7c5d963..24c5dee917 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1006,7 +1006,7 @@ config BOOT_ELF32
 config MIPS_L1_CACHE_SHIFT
 	int
 	default "4" if MACH_DECSTATION
-	default "7" if SGI_IP27 || SGI_IP28 || SNI_RM
+	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
 	default "4" if PMC_MSP4200_EVAL
 	default "5"