From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 20 Mar 2007 13:56:50 +0000 (+0000)
Subject: [MIPS] Fix pipeline hazard.
X-Git-Tag: v2.6.21-rc5~14
X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=7605b3906192a171e651076325b1ed1d5ea57ec9;p=linux-2.6

[MIPS] Fix pipeline hazard.

In the the sequence:
        ei
        ..
        mfc0    $x, $status

the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 50073157a6..e50c77e69c 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -52,6 +52,7 @@ ASMMACRO(tlb_probe_hazard,
 	 _ehb
 	)
 ASMMACRO(irq_enable_hazard,
+	 _ehb
 	)
 ASMMACRO(irq_disable_hazard,
 	_ehb