From: Stefan Roese <sr@denx.de>
Date: Tue, 1 Apr 2008 13:45:00 +0000 (+1100)
Subject: [POWERPC] 4xx: Fix PESDRn_UTLSET1 register setup on 460EX/GT
X-Git-Tag: v2.6.26-rc1~1125^2~83
X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5f91925c89c39e77c170de9366ffa5144a8dd8ec;p=linux-2.6

[POWERPC] 4xx: Fix PESDRn_UTLSET1 register setup on 460EX/GT

The patch fixes a bug, where the PESDRn_UTLSET1 register was setup
wrongly resulting in a non working PCIe port 1. With this fix both
PCIe ports work fine again.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
---

diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index aa856ea9fe..1814adbd22 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -785,19 +785,17 @@ static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 	u32 val;
 	u32 utlset1;
 
-	if (port->endpoint) {
+	if (port->endpoint)
 		val = PTYPE_LEGACY_ENDPOINT << 20;
-		utlset1 = 0x20222222;
-	} else {
+	else
 		val = PTYPE_ROOT_PORT << 20;
-		utlset1 = 0x21222222;
-	}
 
 	if (port->index == 0) {
 		val |= LNKW_X1 << 12;
+		utlset1 = 0x20000000;
 	} else {
 		val |= LNKW_X4 << 12;
-		utlset1 |= 0x00101101;
+		utlset1 = 0x20101101;
 	}
 
 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);