From: Mauro Carvalho Chehab <mchehab@infradead.org>
Date: Fri, 18 Apr 2008 00:44:58 +0000 (-0300)
Subject: V4L/DVB (7613): em28xx: rename registers
X-Git-Tag: v2.6.26-rc1~1084^2~110
X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=41facaa4b63cc1a0ff5a900149a29942d47e1491;p=linux-2.6

V4L/DVB (7613): em28xx: rename registers

Now, all registers will follow the same convension:

EM28XX_R<reg_number>_<reg_name>

This allows to associate a register with its value, and also with a canonical
name. Also, registers that are specific to a given chip were renamed accordingly,
as EM2800_foo (for 2800 only registers) or EM2880_foo (for registers that started
to appear on em2880).

Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
---

diff --git a/drivers/media/video/em28xx/em28xx-cards.c b/drivers/media/video/em28xx/em28xx-cards.c
index cbf6e179ac..ed50b4e552 100644
--- a/drivers/media/video/em28xx/em28xx-cards.c
+++ b/drivers/media/video/em28xx/em28xx-cards.c
@@ -437,17 +437,17 @@ MODULE_DEVICE_TABLE(usb, em28xx_id_table);
 /* Board Hauppauge WinTV HVR 900 analog */
 struct em28xx_reg_seq hauppauge_wintv_hvr_900_analog[] = {
 	{  -1,		-1,     6},
-	{EM_R08_GPIO,	0x2d,  10},
-	{EM_R08_GPIO,	0x3d,   5},
+	{EM28XX_R08_GPIO,	0x2d,  10},
+	{EM28XX_R08_GPIO,	0x3d,   5},
 	{  -1,		-1,    -1},
 };
 /* Board Hauppauge WinTV HVR 900 digital */
 struct em28xx_reg_seq hauppauge_wintv_hvr_900_digital[] = {
 	{  -1,		-1,     6},
-	{EM_R08_GPIO,	0x2e,   6},
-	{EM_R08_GPIO,	0x3e,   6},
-	{EM_R04_GPO,	0x04,  10},
-	{EM_R04_GPO,	0x0c,  10},
+	{EM28XX_R08_GPIO,	0x2e,   6},
+	{EM28XX_R08_GPIO,	0x3e,   6},
+	{EM2880_R04_GPO,	0x04,  10},
+	{EM2880_R04_GPO,	0x0c,  10},
 	{ -1,    -1,  -1},
 };
 
@@ -528,7 +528,7 @@ void em28xx_pre_card_setup(struct em28xx *dev)
 	int rc;
 
 	dev->wait_after_write = 5;
-	rc = em28xx_read_reg(dev, CHIPID_REG);
+	rc = em28xx_read_reg(dev, EM28XX_R0A_CHIPID);
 	if (rc > 0) {
 		switch (rc) {
 		case CHIP_ID_EM2883:
@@ -547,8 +547,8 @@ void em28xx_pre_card_setup(struct em28xx *dev)
 	case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900:
 	case EM2880_BOARD_TERRATEC_HYBRID_XS:
 	case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950:
-		em28xx_write_regs(dev, XCLK_REG, "\x27", 1);
-		em28xx_write_regs(dev, I2C_CLK_REG, "\x40", 1);
+		em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
+		em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
 		em28xx_write_regs(dev, 0x08, "\xff", 1);
 		em28xx_write_regs(dev, 0x04, "\x00", 1);
 		msleep(100);
diff --git a/drivers/media/video/em28xx/em28xx-core.c b/drivers/media/video/em28xx/em28xx-core.c
index e47b206187..01d5f44268 100644
--- a/drivers/media/video/em28xx/em28xx-core.c
+++ b/drivers/media/video/em28xx/em28xx-core.c
@@ -194,17 +194,17 @@ static int em28xx_write_ac97(struct em28xx *dev, u8 reg, u8 *val)
 	int ret, i;
 	u8 addr = reg & 0x7f;
 
-	ret = em28xx_write_regs(dev, AC97LSB_REG, val, 2);
+	ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, val, 2);
 	if (ret < 0)
 		return ret;
 
-	ret = em28xx_write_regs(dev, AC97ADDR_REG, &addr, 1);
+	ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
 	if (ret < 0)
 		return ret;
 
 	/* Wait up to 50 ms for AC97 command to complete */
 	for (i = 0; i < 10; i++) {
-		ret = em28xx_read_reg(dev, AC97BUSY_REG);
+		ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
 		if (ret < 0)
 			return ret;
 
@@ -230,7 +230,7 @@ static int em28xx_set_audio_source(struct em28xx *dev)
 		else
 			input = EM2800_AUDIO_SRC_TUNER;
 
-		ret = em28xx_write_regs(dev, EM2800_AUDIOSRC_REG, &input, 1);
+		ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
 		if (ret < 0)
 			return ret;
 	}
@@ -256,7 +256,7 @@ static int em28xx_set_audio_source(struct em28xx *dev)
 		}
 	}
 
-	ret = em28xx_write_reg_bits(dev, AUDIOSRC_REG, input, 0xc0);
+	ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
 	if (ret < 0)
 		return ret;
 	msleep(5);
@@ -264,11 +264,11 @@ static int em28xx_set_audio_source(struct em28xx *dev)
 	/* Sets AC97 mixer registers
 	   This is seems to be needed, even for non-ac97 configs
 	 */
-	ret = em28xx_write_ac97(dev, VIDEO_AC97, video);
+	ret = em28xx_write_ac97(dev, EM28XX_R14_VIDEO_AC97, video);
 	if (ret < 0)
 		return ret;
 
-	ret = em28xx_write_ac97(dev, LINE_IN_AC97, line);
+	ret = em28xx_write_ac97(dev, EM28XX_R10_LINE_IN_AC97, line);
 
 	return ret;
 }
@@ -284,7 +284,7 @@ int em28xx_audio_analog_set(struct em28xx *dev)
 
 	/* Mute */
 	s[1] |= 0x80;
-	ret = em28xx_write_ac97(dev, MASTER_AC97, s);
+	ret = em28xx_write_ac97(dev, EM28XX_R02_MASTER_AC97, s);
 
 	if (ret < 0)
 		return ret;
@@ -295,7 +295,7 @@ int em28xx_audio_analog_set(struct em28xx *dev)
 	if (!dev->mute)
 		xclk |= 0x80;
 
-	ret = em28xx_write_reg_bits(dev, XCLK_REG, xclk, 0xa7);
+	ret = em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, xclk, 0xa7);
 	if (ret < 0)
 		return ret;
 	msleep(10);
@@ -306,7 +306,7 @@ int em28xx_audio_analog_set(struct em28xx *dev)
 	/* Unmute device */
 	if (!dev->mute)
 		s[1] &= ~0x80;
-	ret = em28xx_write_ac97(dev, MASTER_AC97, s);
+	ret = em28xx_write_ac97(dev, EM28XX_R02_MASTER_AC97, s);
 
 	return ret;
 }
@@ -314,20 +314,20 @@ EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
 
 int em28xx_colorlevels_set_default(struct em28xx *dev)
 {
-	em28xx_write_regs(dev, YGAIN_REG, "\x10", 1);	/* contrast */
-	em28xx_write_regs(dev, YOFFSET_REG, "\x00", 1);	/* brightness */
-	em28xx_write_regs(dev, UVGAIN_REG, "\x10", 1);	/* saturation */
-	em28xx_write_regs(dev, UOFFSET_REG, "\x00", 1);
-	em28xx_write_regs(dev, VOFFSET_REG, "\x00", 1);
-	em28xx_write_regs(dev, SHARPNESS_REG, "\x00", 1);
-
-	em28xx_write_regs(dev, GAMMA_REG, "\x20", 1);
-	em28xx_write_regs(dev, RGAIN_REG, "\x20", 1);
-	em28xx_write_regs(dev, GGAIN_REG, "\x20", 1);
-	em28xx_write_regs(dev, BGAIN_REG, "\x20", 1);
-	em28xx_write_regs(dev, ROFFSET_REG, "\x00", 1);
-	em28xx_write_regs(dev, GOFFSET_REG, "\x00", 1);
-	return em28xx_write_regs(dev, BOFFSET_REG, "\x00", 1);
+	em28xx_write_regs(dev, EM28XX_R20_YGAIN, "\x10", 1);	/* contrast */
+	em28xx_write_regs(dev, EM28XX_R21_YOFFSET, "\x00", 1);	/* brightness */
+	em28xx_write_regs(dev, EM28XX_R22_UVGAIN, "\x10", 1);	/* saturation */
+	em28xx_write_regs(dev, EM28XX_R23_UOFFSET, "\x00", 1);
+	em28xx_write_regs(dev, EM28XX_R24_VOFFSET, "\x00", 1);
+	em28xx_write_regs(dev, EM28XX_R25_SHARPNESS, "\x00", 1);
+
+	em28xx_write_regs(dev, EM28XX_R14_GAMMA, "\x20", 1);
+	em28xx_write_regs(dev, EM28XX_R15_RGAIN, "\x20", 1);
+	em28xx_write_regs(dev, EM28XX_R16_GGAIN, "\x20", 1);
+	em28xx_write_regs(dev, EM28XX_R17_BGAIN, "\x20", 1);
+	em28xx_write_regs(dev, EM28XX_R18_ROFFSET, "\x00", 1);
+	em28xx_write_regs(dev, EM28XX_R19_GOFFSET, "\x00", 1);
+	return em28xx_write_regs(dev, EM28XX_R1A_BOFFSET, "\x00", 1);
 }
 
 int em28xx_capture_start(struct em28xx *dev, int start)
@@ -335,14 +335,14 @@ int em28xx_capture_start(struct em28xx *dev, int start)
 	int rc;
 	/* FIXME: which is the best order? */
 	/* video registers are sampled by VREF */
-	rc = em28xx_write_reg_bits(dev, USBSUSP_REG,
+	rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
 				   start ? 0x10 : 0x00, 0x10);
 	if (rc < 0)
 		return rc;
 
 	if (!start) {
 		/* disable video capture */
-		rc = em28xx_write_regs(dev, VINENABLE_REG, "\x27", 1);
+		rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x27", 1);
 		return rc;
 	}
 
@@ -350,9 +350,9 @@ int em28xx_capture_start(struct em28xx *dev, int start)
 	rc = em28xx_write_regs_req(dev, 0x00, 0x48, "\x00", 1);
 
 	if (dev->mode == EM28XX_ANALOG_MODE)
-		rc = em28xx_write_regs(dev, VINENABLE_REG, "\x67", 1);
+		rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x67", 1);
 	else
-		rc = em28xx_write_regs(dev, VINENABLE_REG, "\x37", 1);
+		rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x37", 1);
 
 	msleep(6);
 
@@ -361,9 +361,9 @@ int em28xx_capture_start(struct em28xx *dev, int start)
 
 int em28xx_outfmt_set_yuv422(struct em28xx *dev)
 {
-	em28xx_write_regs(dev, OUTFMT_REG, "\x34", 1);
-	em28xx_write_regs(dev, VINMODE_REG, "\x10", 1);
-	return em28xx_write_regs(dev, VINCTRL_REG, "\x11", 1);
+	em28xx_write_regs(dev, EM28XX_R27_OUTFMT, "\x34", 1);
+	em28xx_write_regs(dev, EM28XX_R10_VINMODE, "\x10", 1);
+	return em28xx_write_regs(dev, EM28XX_R11_VINCTRL, "\x11", 1);
 }
 
 static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
@@ -372,10 +372,10 @@ static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
 	em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
 			xmin, ymin, xmax, ymax);
 
-	em28xx_write_regs(dev, XMIN_REG, &xmin, 1);
-	em28xx_write_regs(dev, XMAX_REG, &xmax, 1);
-	em28xx_write_regs(dev, YMIN_REG, &ymin, 1);
-	return em28xx_write_regs(dev, YMAX_REG, &ymax, 1);
+	em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
+	em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
+	em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
+	return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
 }
 
 static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
@@ -389,11 +389,11 @@ static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
 			(width | (overflow & 2) << 7),
 			(height | (overflow & 1) << 8));
 
-	em28xx_write_regs(dev, HSTART_REG, &hstart, 1);
-	em28xx_write_regs(dev, VSTART_REG, &vstart, 1);
-	em28xx_write_regs(dev, CWIDTH_REG, &cwidth, 1);
-	em28xx_write_regs(dev, CHEIGHT_REG, &cheight, 1);
-	return em28xx_write_regs(dev, OFLOW_REG, &overflow, 1);
+	em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
+	em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
+	em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
+	em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
+	return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
 }
 
 static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
@@ -406,15 +406,15 @@ static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
 		u8 buf[2];
 		buf[0] = h;
 		buf[1] = h >> 8;
-		em28xx_write_regs(dev, HSCALELOW_REG, (char *)buf, 2);
+		em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
 		buf[0] = v;
 		buf[1] = v >> 8;
-		em28xx_write_regs(dev, VSCALELOW_REG, (char *)buf, 2);
+		em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
 		/* it seems that both H and V scalers must be active
 		   to work correctly */
 		mode = (h || v)? 0x30: 0x00;
 	}
-	return em28xx_write_reg_bits(dev, COMPR_REG, mode, 0x30);
+	return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
 }
 
 /* FIXME: this only function read values from dev */
diff --git a/drivers/media/video/em28xx/em28xx-reg.h b/drivers/media/video/em28xx/em28xx-reg.h
index 02eb2b171b..9058bed079 100644
--- a/drivers/media/video/em28xx/em28xx-reg.h
+++ b/drivers/media/video/em28xx/em28xx-reg.h
@@ -13,68 +13,68 @@
 #define EM_GPO_3   (1 << 3)
 
 /* em2800 registers */
-#define EM2800_AUDIOSRC_REG 0x08
+#define EM2800_R08_AUDIOSRC 0x08
 
 /* em28xx registers */
 
 	/* GPIO/GPO registers */
-#define EM_R04_GPO	0x04    /* em2880-em2883 only */
-#define EM_R08_GPIO	0x08	/* em2820 or upper */
-
-#define I2C_CLK_REG	0x06
-#define CHIPID_REG	0x0a
-#define USBSUSP_REG	0x0c	/* */
-
-#define AUDIOSRC_REG	0x0e
-#define XCLK_REG	0x0f
-
-#define VINMODE_REG	0x10
-#define VINCTRL_REG	0x11
-#define VINENABLE_REG	0x12	/* */
-
-#define GAMMA_REG	0x14
-#define RGAIN_REG	0x15
-#define GGAIN_REG	0x16
-#define BGAIN_REG	0x17
-#define ROFFSET_REG	0x18
-#define GOFFSET_REG	0x19
-#define BOFFSET_REG	0x1a
-
-#define OFLOW_REG	0x1b
-#define HSTART_REG	0x1c
-#define VSTART_REG	0x1d
-#define CWIDTH_REG	0x1e
-#define CHEIGHT_REG	0x1f
-
-#define YGAIN_REG	0x20
-#define YOFFSET_REG	0x21
-#define UVGAIN_REG	0x22
-#define UOFFSET_REG	0x23
-#define VOFFSET_REG	0x24
-#define SHARPNESS_REG	0x25
-
-#define COMPR_REG	0x26
-#define OUTFMT_REG	0x27
-
-#define XMIN_REG	0x28
-#define XMAX_REG	0x29
-#define YMIN_REG	0x2a
-#define YMAX_REG	0x2b
-
-#define HSCALELOW_REG	0x30
-#define HSCALEHIGH_REG	0x31
-#define VSCALELOW_REG	0x32
-#define VSCALEHIGH_REG	0x33
-
-#define AC97LSB_REG	0x40
-#define AC97MSB_REG	0x41
-#define AC97ADDR_REG	0x42
-#define AC97BUSY_REG	0x43
+#define EM2880_R04_GPO	0x04    /* em2880-em2883 only */
+#define EM28XX_R08_GPIO	0x08	/* em2820 or upper */
+
+#define EM28XX_R06_I2C_CLK	0x06
+#define EM28XX_R0A_CHIPID	0x0a
+#define EM28XX_R0C_USBSUSP	0x0c	/* */
+
+#define EM28XX_R0E_AUDIOSRC	0x0e
+#define EM28XX_R0F_XCLK	0x0f
+
+#define EM28XX_R10_VINMODE	0x10
+#define EM28XX_R11_VINCTRL	0x11
+#define EM28XX_R12_VINENABLE	0x12	/* */
+
+#define EM28XX_R14_GAMMA	0x14
+#define EM28XX_R15_RGAIN	0x15
+#define EM28XX_R16_GGAIN	0x16
+#define EM28XX_R17_BGAIN	0x17
+#define EM28XX_R18_ROFFSET	0x18
+#define EM28XX_R19_GOFFSET	0x19
+#define EM28XX_R1A_BOFFSET	0x1a
+
+#define EM28XX_R1B_OFLOW	0x1b
+#define EM28XX_R1C_HSTART	0x1c
+#define EM28XX_R1D_VSTART	0x1d
+#define EM28XX_R1E_CWIDTH	0x1e
+#define EM28XX_R1F_CHEIGHT	0x1f
+
+#define EM28XX_R20_YGAIN	0x20
+#define EM28XX_R21_YOFFSET	0x21
+#define EM28XX_R22_UVGAIN	0x22
+#define EM28XX_R23_UOFFSET	0x23
+#define EM28XX_R24_VOFFSET	0x24
+#define EM28XX_R25_SHARPNESS	0x25
+
+#define EM28XX_R26_COMPR	0x26
+#define EM28XX_R27_OUTFMT	0x27
+
+#define EM28XX_R28_XMIN	0x28
+#define EM28XX_R29_XMAX	0x29
+#define EM28XX_R2A_YMIN	0x2a
+#define EM28XX_R2B_YMAX	0x2b
+
+#define EM28XX_R30_HSCALELOW	0x30
+#define EM28XX_R31_HSCALEHIGH	0x31
+#define EM28XX_R32_VSCALELOW	0x32
+#define EM28XX_R33_VSCALEHIGH	0x33
+
+#define EM28XX_R40_AC97LSB	0x40
+#define EM28XX_R41_AC97MSB	0x41
+#define EM28XX_R42_AC97ADDR	0x42
+#define EM28XX_R43_AC97BUSY	0x43
 
 /* em202 registers */
-#define MASTER_AC97	0x02
-#define LINE_IN_AC97    0x10
-#define VIDEO_AC97	0x14
+#define EM28XX_R02_MASTER_AC97	0x02
+#define EM28XX_R10_LINE_IN_AC97    0x10
+#define EM28XX_R14_VIDEO_AC97	0x14
 
 /* register settings */
 #define EM2800_AUDIO_SRC_TUNER  0x0d
diff --git a/drivers/media/video/em28xx/em28xx-video.c b/drivers/media/video/em28xx/em28xx-video.c
index a8aa09c5bc..fb533fda21 100644
--- a/drivers/media/video/em28xx/em28xx-video.c
+++ b/drivers/media/video/em28xx/em28xx-video.c
@@ -1142,9 +1142,9 @@ static int vidioc_s_frequency(struct file *file, void *priv,
 static int em28xx_reg_len(int reg)
 {
 	switch (reg) {
-	case AC97LSB_REG:
-	case HSCALELOW_REG:
-	case VSCALELOW_REG:
+	case EM28XX_R40_AC97LSB:
+	case EM28XX_R30_HSCALELOW:
+	case EM28XX_R32_VSCALELOW:
 		return 2;
 	default:
 		return 1;
diff --git a/drivers/media/video/em28xx/em28xx.h b/drivers/media/video/em28xx/em28xx.h
index 2188bc44c4..e4a56d8dfc 100644
--- a/drivers/media/video/em28xx/em28xx.h
+++ b/drivers/media/video/em28xx/em28xx.h
@@ -500,73 +500,73 @@ int em28xx_get_key_pinnacle_usb_grey(struct IR_i2c *ir, u32 *ir_key,
 static inline int em28xx_compression_disable(struct em28xx *dev)
 {
 	/* side effect of disabling scaler and mixer */
-	return em28xx_write_regs(dev, COMPR_REG, "\x00", 1);
+	return em28xx_write_regs(dev, EM28XX_R26_COMPR, "\x00", 1);
 }
 
 static inline int em28xx_contrast_get(struct em28xx *dev)
 {
-	return em28xx_read_reg(dev, YGAIN_REG) & 0x1f;
+	return em28xx_read_reg(dev, EM28XX_R20_YGAIN) & 0x1f;
 }
 
 static inline int em28xx_brightness_get(struct em28xx *dev)
 {
-	return em28xx_read_reg(dev, YOFFSET_REG);
+	return em28xx_read_reg(dev, EM28XX_R21_YOFFSET);
 }
 
 static inline int em28xx_saturation_get(struct em28xx *dev)
 {
-	return em28xx_read_reg(dev, UVGAIN_REG) & 0x1f;
+	return em28xx_read_reg(dev, EM28XX_R22_UVGAIN) & 0x1f;
 }
 
 static inline int em28xx_u_balance_get(struct em28xx *dev)
 {
-	return em28xx_read_reg(dev, UOFFSET_REG);
+	return em28xx_read_reg(dev, EM28XX_R23_UOFFSET);
 }
 
 static inline int em28xx_v_balance_get(struct em28xx *dev)
 {
-	return em28xx_read_reg(dev, VOFFSET_REG);
+	return em28xx_read_reg(dev, EM28XX_R24_VOFFSET);
 }
 
 static inline int em28xx_gamma_get(struct em28xx *dev)
 {
-	return em28xx_read_reg(dev, GAMMA_REG) & 0x3f;
+	return em28xx_read_reg(dev, EM28XX_R14_GAMMA) & 0x3f;
 }
 
 static inline int em28xx_contrast_set(struct em28xx *dev, s32 val)
 {
 	u8 tmp = (u8) val;
-	return em28xx_write_regs(dev, YGAIN_REG, &tmp, 1);
+	return em28xx_write_regs(dev, EM28XX_R20_YGAIN, &tmp, 1);
 }
 
 static inline int em28xx_brightness_set(struct em28xx *dev, s32 val)
 {
 	u8 tmp = (u8) val;
-	return em28xx_write_regs(dev, YOFFSET_REG, &tmp, 1);
+	return em28xx_write_regs(dev, EM28XX_R21_YOFFSET, &tmp, 1);
 }
 
 static inline int em28xx_saturation_set(struct em28xx *dev, s32 val)
 {
 	u8 tmp = (u8) val;
-	return em28xx_write_regs(dev, UVGAIN_REG, &tmp, 1);
+	return em28xx_write_regs(dev, EM28XX_R22_UVGAIN, &tmp, 1);
 }
 
 static inline int em28xx_u_balance_set(struct em28xx *dev, s32 val)
 {
 	u8 tmp = (u8) val;
-	return em28xx_write_regs(dev, UOFFSET_REG, &tmp, 1);
+	return em28xx_write_regs(dev, EM28XX_R23_UOFFSET, &tmp, 1);
 }
 
 static inline int em28xx_v_balance_set(struct em28xx *dev, s32 val)
 {
 	u8 tmp = (u8) val;
-	return em28xx_write_regs(dev, VOFFSET_REG, &tmp, 1);
+	return em28xx_write_regs(dev, EM28XX_R24_VOFFSET, &tmp, 1);
 }
 
 static inline int em28xx_gamma_set(struct em28xx *dev, s32 val)
 {
 	u8 tmp = (u8) val;
-	return em28xx_write_regs(dev, GAMMA_REG, &tmp, 1);
+	return em28xx_write_regs(dev, EM28XX_R14_GAMMA, &tmp, 1);
 }
 
 /*FIXME: maxw should be dependent of alt mode */