From: Russ Anderson Date: Wed, 25 Oct 2006 19:18:27 +0000 (-0500) Subject: [IA64] Add dp bit to cache and bus check structs X-Git-Tag: v2.6.20-rc1~34^2~412^2~2^2~10 X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=323cbb09917024cab522bc7ce5c343659cbe8818;p=linux-2.6 [IA64] Add dp bit to cache and bus check structs Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's Manual" (January 2006) adds a dp bit to the cache_check and bus_check fields (pages 2:401-2:404). This patch gets the structs back in sync with the spec. Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck --- diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h index 4283ddcc25..b6d4f6f0c3 100644 --- a/include/asm-ia64/pal.h +++ b/include/asm-ia64/pal.h @@ -487,10 +487,12 @@ typedef struct pal_cache_check_info_s { * error occurred */ wiv : 1, /* Way field valid */ - reserved2 : 10, + reserved2 : 1, + dp : 1, /* Data poisoned on MBE */ + reserved3 : 8, index : 20, /* Cache line index */ - reserved3 : 2, + reserved4 : 2, is : 1, /* instruction set (1 == ia32) */ iv : 1, /* instruction set field valid */ @@ -557,7 +559,7 @@ typedef struct pal_bus_check_info_s { type : 8, /* Bus xaction type*/ sev : 5, /* Bus error severity*/ hier : 2, /* Bus hierarchy level */ - reserved1 : 1, + dp : 1, /* Data poisoned on MBE */ bsi : 8, /* Bus error status * info */