[MIPS] Malta: fix oversized lines in malta_int.c

This patch fixes all "line over 80 characters" warnings found
in arch/mips/mips-boards/malta/malta_int.c by the checkpatch.pl
script.

No functional changes introduced.

Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 6d371f4ac35827bd68f74888adcc0694af21b974..1b4b9c507e28684b42da22929cd58f392f8aefd6 100644 (file)
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -304,17 +304,25 @@ void __init arch_init_irq(void)
        case MIPS_REVISION_SCON_SOCIT:
        case MIPS_REVISION_SCON_ROCIT:
                if (cpu_has_veic)
-                       init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
+                       init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
+                                       MSC01E_INT_BASE, msc_eicirqmap,
+                                       msc_nr_eicirqs);
                else
-                       init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
+                       init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
+                                       MSC01C_INT_BASE, msc_irqmap,
+                                       msc_nr_irqs);
                break;
 
        case MIPS_REVISION_SCON_SOCITSC:
        case MIPS_REVISION_SCON_SOCITSCP:
                if (cpu_has_veic)
-                       init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
+                       init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
+                                       MSC01E_INT_BASE, msc_eicirqmap,
+                                       msc_nr_eicirqs);
                else
-                       init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
+                       init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
+                                       MSC01C_INT_BASE, msc_irqmap,
+                                       msc_nr_irqs);
        }
 
        if (cpu_has_veic) {
@@ -345,11 +353,13 @@ void __init arch_init_irq(void)
                }
 #else /* Not SMTC */
                setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
-               setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
+               setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
+                                               &corehi_irqaction);
 #endif /* CONFIG_MIPS_MT_SMTC */
        }
        else {
                setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
-               setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
+               setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
+                                               &corehi_irqaction);
        }
 }