[ARM] nommu: manage the CP15 things

All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:

     Related operation	Safe condition
  a. any CP15 access	!CPU_CP15
  b. alignment trap	CPU_CP15_MMU
  c. D-cache(C-bit)	CPU_CP15
  d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
				CPU_ARM720 || CPU_ARM740 ||
				CPU_XSCALE || CPU_XSC3 )
  e. alternate vector	CPU_CP15 && !CPU_ARM740
  f. TTB		CPU_CP15_MMU
  g. Domain		CPU_CP15_MMU
  h. FSR/FAR		CPU_CP15_MMU

For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0810d27c039e44b42f18011bab024c6117dc2ec5..2673fee3281cd0f45c433a6efe7ace34900041f1 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -621,6 +621,7 @@ config LEDS_CPU
 
 config ALIGNMENT_TRAP
        bool
+       depends on CPU_CP15_MMU
        default y if !ARCH_EBSA110
        help
          ARM processors can not fetch/store information which is not
@@ -852,7 +853,7 @@ source "drivers/base/Kconfig"
 
 source "drivers/connector/Kconfig"
 
-if ALIGNMENT_TRAP
+if ALIGNMENT_TRAP || !CPU_CP15_MMU
 source "drivers/mtd/Kconfig"
 endif
 

diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu
index e1574be2ded614e05633c715381df9086d69f776..f087376748d12253bb9f0414c6c742dfd6eb0b89 100644 (file)
--- a/arch/arm/Kconfig-nommu
+++ b/arch/arm/Kconfig-nommu
@@ -25,6 +25,14 @@ config FLASH_SIZE
        hex 'FLASH Size' if SET_MEM_PARAM
        default 0x00400000
 
+config PROCESSOR_ID
+       hex
+       default 0x00007700
+       depends on !CPU_CP15
+       help
+         If processor has no CP15 register, this processor ID is
+         used instead of the auto-probing which utilizes the register.
+
 config REMAP_VECTORS_TO_RAM
        bool 'Install vectors to the begining of RAM' if DRAM_BASE
        depends on DRAM_BASE

diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 2adc1527e0ebc9d7a3d4936b0eb4e767381e2e84..adddc71316852f5001314faf10678f5fc4e3ef8d 100644 (file)
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -51,7 +51,11 @@ OBJS         += head-at91rm9200.o
 endif
 
 ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
+ifeq ($(CONFIG_CPU_CP15),y)
 OBJS           += big-endian.o
+else
+# The endian should be set by h/w design.
+endif
 endif
 
 #

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 75df1f764a10eff4af12c5e5e55240d42f6da941..e5ab51b9cceb1bdfd155c9824ba6364d21cc1977 100644 (file)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -82,9 +82,11 @@
                kphex   r6, 8           /* processor id */
                kputc   #':'
                kphex   r7, 8           /* architecture id */
+#ifdef CONFIG_CPU_CP15
                kputc   #':'
                mrc     p15, 0, r0, c1, c0
                kphex   r0, 8           /* control reg */
+#endif
                kputc   #'\n'
                kphex   r5, 8           /* decompressed kernel start */
                kputc   #'-'
@@ -507,7 +509,11 @@ call_kernel:       bl      cache_clean_flush
  */
 
 call_cache_fn: adr     r12, proc_types
+#ifdef CONFIG_CPU_CP15
                mrc     p15, 0, r6, c0, c0      @ get processor ID
+#else
+               ldr     r6, =CONFIG_PROCESSOR_ID
+#endif
 1:             ldr     r1, [r12, #0]           @ get value
                ldr     r2, [r12, #4]           @ get mask
                eor     r1, r1, r6              @ (real ^ match)

diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index ac9eb3d30518ade76e1b01965fb969d90f856950..698a537915dd4ba5286f4909988934b8ad2d87f1 100644 (file)
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -9,7 +9,6 @@
  * published by the Free Software Foundation.
  *
  *  Common kernel startup code (non-paged MM)
- *    for 32-bit CPUs which has a process ID register(CP15).
  *
  */
 #include <linux/linkage.h>
@@ -40,7 +39,11 @@
 ENTRY(stext)
        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
                                                @ and irqs disabled
+#ifndef CONFIG_CPU_CP15
+       ldr     r9, =CONFIG_PROCESSOR_ID
+#else
        mrc     p15, 0, r9, c0, c0              @ get processor id
+#endif
        bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
        movs    r10, r5                         @ invalid processor (r5=0)?
        beq     __error_p                               @ yes, error 'p'
@@ -58,6 +61,7 @@ ENTRY(stext)
  */
        .type   __after_proc_init, %function
 __after_proc_init:
+#ifdef CONFIG_CPU_CP15
        mrc     p15, 0, r0, c1, c0, 0           @ read control reg
 #ifdef CONFIG_ALIGNMENT_TRAP
        orr     r0, r0, #CR_A
@@ -74,6 +78,7 @@ __after_proc_init:
        bic     r0, r0, #CR_I
 #endif
        mcr     p15, 0, r0, c1, c0, 0           @ write control reg
+#endif /* CONFIG_CPU_CP15 */
 
        mov     pc, r13                         @ clear the BSS and jump
                                                @ to start_kernel

diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 3079535afccd4be9daf1219c101ac8bc0959e7c7..bf35c178a8772d232fc5e5e1eb0e5ba91449a2fd 100644 (file)
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -221,16 +221,26 @@ void __show_regs(struct pt_regs *regs)
                processor_modes[processor_mode(regs)],
                thumb_mode(regs) ? " (T)" : "",
                get_fs() == get_ds() ? "kernel" : "user");
+#if CONFIG_CPU_CP15
        {
-               unsigned int ctrl, transbase, dac;
+               unsigned int ctrl;
                  __asm__ (
                "       mrc p15, 0, %0, c1, c0\n"
-               "       mrc p15, 0, %1, c2, c0\n"
-               "       mrc p15, 0, %2, c3, c0\n"
-               : "=r" (ctrl), "=r" (transbase), "=r" (dac));
-               printk("Control: %04X  Table: %08X  DAC: %08X\n",
-                       ctrl, transbase, dac);
+               : "=r" (ctrl));
+               printk("Control: %04X\n", ctrl);
        }
+#ifdef CONFIG_CPU_CP15_MMU
+       {
+               unsigned int transbase, dac;
+                 __asm__ (
+               "       mrc p15, 0, %0, c2, c0\n"
+               "       mrc p15, 0, %1, c3, c0\n"
+               : "=r" (transbase), "=r" (dac));
+               printk("Table: %08X  DAC: %08X\n",
+                       transbase, dac);
+       }
+#endif
+#endif
 }
 
 void show_regs(struct pt_regs * regs)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c7fb835c148ce53cad348f6cc58261fd9e6dae95..0ac11ea84508bd3d81854beb683c377f5089b93c 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -445,15 +445,15 @@ config CPU_BIG_ENDIAN
          of your chipset/board/processor.
 
 config CPU_ICACHE_DISABLE
-       bool "Disable I-Cache"
-       depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
+       bool "Disable I-Cache (I-bit)"
+       depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
        help
          Say Y here to disable the processor instruction cache. Unless
          you have a reason not to or are unsure, say N.
 
 config CPU_DCACHE_DISABLE
-       bool "Disable D-Cache"
-       depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
+       bool "Disable D-Cache (C-bit)"
+       depends on CPU_CP15
        help
          Say Y here to disable the processor data cache. Unless
          you have a reason not to or are unsure, say N.

diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index b8ad5d58ebe2ff11f687704c8f31a86d83014dd3..b2908063ed6aa5be10ebdfd7ee00b37ef5e8021f 100644 (file)
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -29,9 +29,13 @@ ENTRY(v4_flush_user_cache_all)
  *     Clean and invalidate the entire cache.
  */
 ENTRY(v4_flush_kern_cache_all)
+#ifdef CPU_CP15
        mov     r0, #0
        mcr     p15, 0, r0, c7, c7, 0           @ flush ID cache
        mov     pc, lr
+#else
+       /* FALLTHROUGH */
+#endif
 
 /*
  *     flush_user_cache_range(start, end, flags)
@@ -44,9 +48,13 @@ ENTRY(v4_flush_kern_cache_all)
  *     - flags - vma_area_struct flags describing address space
  */
 ENTRY(v4_flush_user_cache_range)
+#ifdef CPU_CP15
        mov     ip, #0
        mcreq   p15, 0, ip, c7, c7, 0           @ flush ID cache
        mov     pc, lr
+#else
+       /* FALLTHROUGH */
+#endif
 
 /*
  *     coherent_kern_range(start, end)
@@ -108,8 +116,10 @@ ENTRY(v4_dma_inv_range)
  *     - end    - virtual end address
  */
 ENTRY(v4_dma_flush_range)
+#ifdef CPU_CP15
        mov     r0, #0
        mcr     p15, 0, r0, c7, c7, 0           @ flush ID cache
+#endif
        /* FALLTHROUGH */
 
 /*

diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index c19c5b009f71f0409e47bafbe53c4933f19d402f..f05fbe31576cbeabb2b6d717698d7cebfdc63b4e 100644 (file)
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -46,6 +46,7 @@
 #define CPUID_TCM      2
 #define CPUID_TLBTYPE  3
 
+#ifdef CONFIG_CPU_CP15
 #define read_cpuid(reg)                                                        \
        ({                                                              \
                unsigned int __val;                                     \
@@ -55,6 +56,9 @@
                    : "cc");                                            \
                __val;                                                  \
        })
+#else
+#define read_cpuid(reg) (processor_id)
+#endif
 
 /*
  * This is used to ensure the compiler did actually allocate the register we