[SPARC64]: Use different cache sizing defaults on SUN4V.

Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/sparc64/kernel/devices.c b/arch/sparc64/kernel/devices.c
index 817132826e099d963cc0af1f776ded23007acffa..71eee392e14146599ee808b9e7e7cd09860ebd3e 100644 (file)
--- a/arch/sparc64/kernel/devices.c
+++ b/arch/sparc64/kernel/devices.c
@@ -200,7 +200,8 @@ void __init device_scan(void)
 
 #ifndef CONFIG_SMP
        {
-               int err, cpu_node;
+               int err, cpu_node, def;
+
                err = cpu_find_by_instance(0, &cpu_node, NULL);
                if (err) {
                        prom_printf("No cpu nodes, cannot continue\n");
@@ -209,21 +210,40 @@ void __init device_scan(void)
                cpu_data(0).clock_tick = prom_getintdefault(cpu_node,
                                                            "clock-frequency",
                                                            0);
+
+               def = ((tlb_type == hypervisor) ?
+                      (8 * 1024) :
+                      (16 * 1024));
                cpu_data(0).dcache_size = prom_getintdefault(cpu_node,
                                                             "dcache-size",
-                                                            16 * 1024);
+                                                            def);
+
+               def = 32;
                cpu_data(0).dcache_line_size =
-                       prom_getintdefault(cpu_node, "dcache-line-size", 32);
+                       prom_getintdefault(cpu_node, "dcache-line-size",
+                                          def);
+
+               def = 16 * 1024;
                cpu_data(0).icache_size = prom_getintdefault(cpu_node,
                                                             "icache-size",
-                                                            16 * 1024);
+                                                            def);
+
+               def = 32;
                cpu_data(0).icache_line_size =
-                       prom_getintdefault(cpu_node, "icache-line-size", 32);
+                       prom_getintdefault(cpu_node, "icache-line-size",
+                                          def);
+
+               def = ((tlb_type == hypervisor) ?
+                      (3 * 1024 * 1024) :
+                      (4 * 1024 * 1024));
                cpu_data(0).ecache_size = prom_getintdefault(cpu_node,
                                                             "ecache-size",
-                                                            4 * 1024 * 1024);
+                                                            def);
+
+               def = 64;
                cpu_data(0).ecache_line_size =
-                       prom_getintdefault(cpu_node, "ecache-line-size", 64);
+                       prom_getintdefault(cpu_node, "ecache-line-size",
+                                          def);
                printk("CPU[0]: Caches "
                       "D[sz(%d):line_sz(%d)] "
                       "I[sz(%d):line_sz(%d)] "

diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index c280e6742b253754dc723626aa44e5e33370ff3d..64046d37bbf048ea8234a7a110bef91956b408ad 100644 (file)
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -78,7 +78,7 @@ void smp_bogo(struct seq_file *m)
 
 void __init smp_store_cpu_info(int id)
 {
-       int cpu_node;
+       int cpu_node, def;
 
        /* multiplier and counter set by
           smp_setup_percpu_timer()  */
@@ -90,18 +90,32 @@ void __init smp_store_cpu_info(int id)
 
        cpu_data(id).idle_volume                = 1;
 
+       def = ((tlb_type == hypervisor) ? (8 * 1024) : (16 * 1024));
        cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
-                                                     16 * 1024);
+                                                     def);
+
+       def = 32;
        cpu_data(id).dcache_line_size =
-               prom_getintdefault(cpu_node, "dcache-line-size", 32);
+               prom_getintdefault(cpu_node, "dcache-line-size", def);
+
+       def = 16 * 1024;
        cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
-                                                     16 * 1024);
+                                                     def);
+
+       def = 32;
        cpu_data(id).icache_line_size =
-               prom_getintdefault(cpu_node, "icache-line-size", 32);
+               prom_getintdefault(cpu_node, "icache-line-size", def);
+
+       def = ((tlb_type == hypervisor) ?
+              (3 * 1024 * 1024) :
+              (4 * 1024 * 1024));
        cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
-                                                     4 * 1024 * 1024);
+                                                     def);
+
+       def = 64;
        cpu_data(id).ecache_line_size =
-               prom_getintdefault(cpu_node, "ecache-line-size", 64);
+               prom_getintdefault(cpu_node, "ecache-line-size", def);
+
        printk("CPU[%d]: Caches "
               "D[sz(%d):line_sz(%d)] "
               "I[sz(%d):line_sz(%d)] "