#include <asm/smp.h>
#include <asm/war.h>
-static __init int __attribute__((unused)) r45k_bvahwbug(void)
+static __init int __maybe_unused r45k_bvahwbug(void)
{
/* XXX: We should probe for the presence of this bug, but we don't. */
return 0;
}
-static __init int __attribute__((unused)) r4k_250MHZhwbug(void)
+static __init int __maybe_unused r4k_250MHZhwbug(void)
{
/* XXX: We should probe for the presence of this bug, but we don't. */
return 0;
}
-static __init int __attribute__((unused)) bcm1250_m3_war(void)
+static __init int __maybe_unused bcm1250_m3_war(void)
{
return BCM1250_M3_WAR;
}
-static __init int __attribute__((unused)) r10000_llsc_war(void)
+static __init int __maybe_unused r10000_llsc_war(void)
{
return R10000_LLSC_WAR;
}
#define i_ehb(buf) i_sll(buf, 0, 0, 3)
#ifdef CONFIG_64BIT
-static __init int __attribute__((unused)) in_compat_space_p(long addr)
+static __init int __maybe_unused in_compat_space_p(long addr)
{
/* Is this address in 32bit compat space? */
return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
}
-static __init int __attribute__((unused)) rel_highest(long val)
+static __init int __maybe_unused rel_highest(long val)
{
return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
}
-static __init int __attribute__((unused)) rel_higher(long val)
+static __init int __maybe_unused rel_higher(long val)
{
return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
}
i_lui(buf, rs, rel_hi(addr));
}
-static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs,
- long addr)
+static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs,
+ long addr)
{
i_LA_mostly(buf, rs, addr);
if (rel_lo(addr))
move_labels(lab, first, end, off);
}
-static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel,
- u32 *addr)
+static __init int __maybe_unused insn_has_bdelay(struct reloc *rel,
+ u32 *addr)
{
for (; rel->lab != label_invalid; rel++) {
if (rel->addr == addr
}
/* convenience functions for labeled branches */
-static void __init __attribute__((unused))
+static void __init __maybe_unused
il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
{
r_mips_pc16(r, *p, l);
i_bltz(p, reg, 0);
}
-static void __init __attribute__((unused)) il_b(u32 **p, struct reloc **r,
- enum label_id l)
+static void __init __maybe_unused il_b(u32 **p, struct reloc **r,
+ enum label_id l)
{
r_mips_pc16(r, *p, l);
i_b(p, 0);
i_beqz(p, reg, 0);
}
-static void __init __attribute__((unused))
+static void __init __maybe_unused
il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
{
r_mips_pc16(r, *p, l);
i_bgezl(p, reg, 0);
}
-static void __init __attribute__((unused))
+static void __init __maybe_unused
il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
{
r_mips_pc16(r, *p, l);
*
* As if we MIPS hackers wouldn't know how to nop pipelines happy ...
*/
-static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p)
+static __init void __maybe_unused build_tlb_probe_entry(u32 **p)
{
switch (current_cpu_data.cputype) {
/* Found by experiment: R4600 v2.0 needs this, too. */
* TMP and PTR are scratch.
* TMP will be clobbered, PTR will hold the pgd entry.
*/
-static __init void __attribute__((unused))
+static __init void __maybe_unused
build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
{
long pgdc = (long)pgd_current;