[ARM] Merge remaining IOP code

Conflicts:
	include/asm-arm/arch-at91rm9200/entry-macro.S

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --cc arch/arm/mach-iop32x/n2100.c
Simple merge

diff --cc include/asm-arm/arch-at91/entry-macro.S
index 76c8cccf73aa18bc6c10dcf82507f5b45078c31c,0000000000000000000000000000000000000000..cc1d850a0788012574c2c44310245789a8b1fbb5
mode 100644,000000..100644
--- 1/include/asm-arm/arch-at91/entry-macro.S
--- /dev/null
+++ b/include/asm-arm/arch-at91/entry-macro.S
@@@ -1,26 -1,0 +1,32 @@@
 +/*
 + * include/asm-arm/arch-at91/entry-macro.S
 + *
 + *  Copyright (C) 2003-2005 SAN People
 + *
 + * Low-level IRQ helper macros for AT91RM9200 platforms
 + *
 + * This file is licensed under the terms of the GNU General Public
 + * License version 2. This program is licensed "as is" without any
 + * warranty of any kind, whether express or implied.
 + */
 +
 +#include <asm/hardware.h>
 +#include <asm/arch/at91_aic.h>
 +
 +      .macro  disable_fiq
 +      .endm
 +
++      .macro  get_irqnr_preamble, base, tmp
++      .endm
++
++      .macro  arch_ret_to_user, tmp1, tmp2
++      .endm
++
 +      .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 +      ldr     \base, =(AT91_VA_BASE_SYS + AT91_AIC)           @ base virtual address of AIC peripheral
 +      ldr     \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)]     @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
 +      ldr     \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)]   @ read interrupt source number
 +      teq     \irqstat, #0                                    @ ISR is 0 when no current interrupt, or spurious interrupt
 +      streq   \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)]     @ not going to be handled further, then ACK it now.
 +      .endm
 +

diff --cc include/asm-arm/arch-imx/entry-macro.S
index 61bb0bdc1b1651744c0b888a5ffd73a8461dd50c,d8cbafa6cc49d25514df36f6d4c7de1486ec8336..0b84e81031c34f75a5d9223001e46626a3c20c31
--- 1/include/asm-arm/arch-imx/entry-macro.S
--- 2/include/asm-arm/arch-imx/entry-macro.S
+++ b/include/asm-arm/arch-imx/entry-macro.S
@@@ -11,15 -11,28 +11,22 @@@
  
                .macro  disable_fiq
                .endm
+ 
+               .macro  get_irqnr_preamble, base, tmp
+               .endm
+ 
+               .macro  arch_ret_to_user, tmp1, tmp2
+               .endm
+ 
  #define AITC_NIVECSR   0x40
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 -              ldr     \irqstat, =IO_ADDRESS(IMX_AITC_BASE)
 +              ldr     \base, =IO_ADDRESS(IMX_AITC_BASE)
                @ Load offset & priority of the highest priority
                @ interrupt pending.
 -              ldr     \irqnr, [\irqstat, #AITC_NIVECSR]
 +              ldr     \irqstat, [\base, #AITC_NIVECSR]
                @ Shift off the priority leaving the offset or
 -              @ "interrupt number"
 -              mov     \irqnr, \irqnr, lsr #16
 -              ldr     \irqstat, =1    @ dummy compare
 -              ldr     \base, =0xFFFF          // invalid interrupt
 -              cmp     \irqnr, \base
 -              bne     1001f
 -              ldr     \irqstat, =0
 -1001:
 -              tst     \irqstat, #1    @ to make the condition code = TRUE
 +              @ "interrupt number", use arithmetic shift to
 +              @ transform illegal source (0xffff) as -1
 +              mov     \irqnr, \irqstat, asr #16
 +              adds    \tmp, \irqnr, #1
                .endm
 -