MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5e1b08b00a33912f4567beb6c8463e4476f1c1d0..d00f8768e2a02023948daf352698ee6bde829c64 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -447,10 +447,10 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
        isa = (config0 & MIPS_CONF_AT) >> 13;
        switch (isa) {
        case 0:
-               c->isa_level = MIPS_CPU_ISA_M32;
+               c->isa_level = MIPS_CPU_ISA_M32R1;
                break;
        case 2:
-               c->isa_level = MIPS_CPU_ISA_M64;
+               c->isa_level = MIPS_CPU_ISA_M64R1;
                break;
        default:
                panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
@@ -568,7 +568,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
                break;
        case PRID_IMP_34K:
                c->cputype = CPU_34K;
-               c->isa_level = MIPS_CPU_ISA_M32;
+               c->isa_level = MIPS_CPU_ISA_M32R1;
                break;
        }
 }
@@ -647,7 +647,7 @@ static inline void cpu_probe_philips(struct cpuinfo_mips *c)
        switch (c->processor_id & 0xff00) {
        case PRID_IMP_PR4450:
                c->cputype = CPU_PR4450;
-               c->isa_level = MIPS_CPU_ISA_M32;
+               c->isa_level = MIPS_CPU_ISA_M32R1;
                break;
        default:
                panic("Unknown Philips Core!"); /* REVISIT: die? */
@@ -690,8 +690,8 @@ __init void cpu_probe(void)
        if (c->options & MIPS_CPU_FPU) {
                c->fpu_id = cpu_get_fpu_id();
 
-               if (c->isa_level == MIPS_CPU_ISA_M32 ||
-                   c->isa_level == MIPS_CPU_ISA_M64) {
+               if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
+                   c->isa_level == MIPS_CPU_ISA_M64R1) {
                        if (c->fpu_id & MIPS_FPIR_3D)
                                c->ases |= MIPS_ASE_MIPS3D;
                }

diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 787ed541d442b2449947825dbdd480d55b6d80bf..174959bf1d595ba46a67aa89db1cf0c9ca692496 100644 (file)
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -628,7 +628,7 @@ void __init time_init(void)
                        mips_hpt_init = c0_hpt_init;
                }
 
-               if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32) ||
+               if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32R1) ||
                         (current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
                         (current_cpu_data.isa_level == MIPS_CPU_ISA_II))
                        /*

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 38223b44d96229d9332c16463eceb1df0bdd534a..422b55fab07ab5b5dfb82341a3380b55696da902 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1183,8 +1183,8 @@ static void __init setup_scache(void)
        if (!sc_present)
                return;
 
-       if ((c->isa_level == MIPS_CPU_ISA_M32 ||
-            c->isa_level == MIPS_CPU_ISA_M64) &&
+       if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
+            c->isa_level == MIPS_CPU_ISA_M64R1) &&
            !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
                panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
 

diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 48eac296060f51c23edcc1d4e7adcf6a6eb88f04..256fe130eae8cc8fd974d9bbf6e59705cd86025c 100644 (file)
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -202,18 +202,15 @@
  * ISA Level encodings
  *
  */
+#define MIPS_CPU_ISA_64BIT     0x00008000
+
 #define MIPS_CPU_ISA_I         0x00000001
 #define MIPS_CPU_ISA_II                0x00000002
-#define MIPS_CPU_ISA_III       0x00008003
-#define MIPS_CPU_ISA_IV                0x00008004
-#define MIPS_CPU_ISA_V         0x00008005
-#define MIPS_CPU_ISA_M32       0x00000020
-#define MIPS_CPU_ISA_M64       0x00008040
-
-/*
- * Bit 15 encodes if an ISA level supports 64-bit operations.
- */
-#define MIPS_CPU_ISA_64BIT     0x00008000
+#define MIPS_CPU_ISA_III       (0x00000003 | MIPS_CPU_ISA_64BIT)
+#define MIPS_CPU_ISA_IV                (0x00000004 | MIPS_CPU_ISA_64BIT)
+#define MIPS_CPU_ISA_V         (0x00000005 | MIPS_CPU_ISA_64BIT)
+#define MIPS_CPU_ISA_M32R1     0x00000020
+#define MIPS_CPU_ISA_M64R1     (0x00000040 | MIPS_CPU_ISA_64BIT)
 
 /*
  * CPU Option encodings