powerpc/85xx: TQM8548: DTS file fixes and cleanup

Due to the missing compatible property for the SOC, the MPC I2C buses are
not found any more. This patch fixes this issue. Furthermore it corrects
the name of the SOC node and adds the missing I2C node for the RTC.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 64d2d5bbcdf189331b8ed024d87e07eba9b1c59f..4199e89b4e50cdf871ca2ff51f74f3e7be7ba541 100644 (file)
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -50,13 +50,14 @@
                reg = <0x00000000 0x00000000>;  // Filled in by U-Boot
        };
 
-       soc8548@a0000000 {
+       soc@a0000000 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xa0000000 0x100000>;
                reg = <0xa0000000 0x1000>;      // CCSRBAR
                bus-frequency = <0>;
+               compatible = "fsl,mpc8548-immr", "simple-bus";
 
                memory-controller@2000 {
                        compatible = "fsl,mpc8548-memory-controller";
@@ -83,6 +84,11 @@
                        interrupts = <43 2>;
                        interrupt-parent = <&mpic>;
                        dfsrr;
+
+                       rtc@68 {
+                               compatible = "dallas,ds1337";
+                               reg = <0x68>;
+                       };
                };
 
                i2c@3100 {

diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 2563112cabd328e73ae174551e06495532ee4628..58ee4185454b233f32f3bca4195303d7ddd5e20f 100644 (file)
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -50,13 +50,14 @@
                reg = <0x00000000 0x00000000>;  // Filled in by U-Boot
        };
 
-       soc8548@e0000000 {
+       soc@e0000000 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xe0000000 0x100000>;
                reg = <0xe0000000 0x1000>;      // CCSRBAR
                bus-frequency = <0>;
+               compatible = "fsl,mpc8548-immr", "simple-bus";
 
                memory-controller@2000 {
                        compatible = "fsl,mpc8548-memory-controller";