Replace snd_vx_delay() with appropriate delay/sleep functions.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
#define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg)
#define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val)
-void snd_vx_delay(vx_core_t *chip, int msec);
-
static inline void vx_reset_dsp(vx_core_t *chip)
{
snd_assert(chip->ops->reset_dsp, return);
MODULE_LICENSE("GPL");
-/*
- * snd_vx_delay - delay for the specified time
- * @xmsec: the time to delay in msec
- */
-void snd_vx_delay(vx_core_t *chip, int xmsec)
-{
- if (! in_interrupt() && xmsec >= 1000 / HZ)
- msleep(xmsec);
- else
- mdelay(xmsec);
-}
-
/*
* vx_check_reg_bit - wait for the specified bit is set/reset on a register
* @reg: register to check
do {
if ((snd_vx_inb(chip, reg) & mask) == bit)
return 0;
- //snd_vx_delay(chip, 10);
+ //msleep(10);
} while (time_after_eq(end_time, jiffies));
snd_printd(KERN_DEBUG "vx_check_reg_bit: timeout, reg=%s, mask=0x%x, val=0x%x\n", reg_names[reg], mask, snd_vx_inb(chip, reg));
return -EIO;
if ((err = snd_vx_load_boot_image(chip, boot)) < 0)
return err;
- snd_vx_delay(chip, 10);
+ msleep(10);
return 0;
}
}
snd_printdd(KERN_DEBUG "checksum = 0x%08x\n", csum);
- snd_vx_delay(chip, 200);
+ msleep(200);
if ((err = vx_wait_isr_bit(chip, ISR_CHK)) < 0)
return err;
EXPORT_SYMBOL(snd_vx_setup_firmware);
EXPORT_SYMBOL(snd_vx_free_firmware);
EXPORT_SYMBOL(snd_vx_irq_handler);
-EXPORT_SYMBOL(snd_vx_delay);
EXPORT_SYMBOL(snd_vx_dsp_boot);
EXPORT_SYMBOL(snd_vx_dsp_load);
EXPORT_SYMBOL(snd_vx_load_boot_image);
/* set the reset dsp bit to 0 */
vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
- snd_vx_delay(_chip, XX_DSP_RESET_WAIT_TIME);
+ mdelay(XX_DSP_RESET_WAIT_TIME);
chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
/* set the reset dsp bit to 1 */
/* XILINX reset (wait at least 1 milisecond between reset on and off). */
vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
vx_inl(chip, CNTRL);
- snd_vx_delay(chip, 10);
+ msleep(10);
vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
vx_inl(chip, CNTRL);
- snd_vx_delay(chip, 10);
+ msleep(10);
if (chip->type == VX_TYPE_BOARD)
port = VX_CNTRL;
}
put_xilinx_data(chip, port, 4, 0xff); /* end signature */
- snd_vx_delay(chip, 200);
+ msleep(200);
/* test after loading (is buggy with VX222) */
if (chip->type != VX_TYPE_BOARD) {
/* Set the reset CODEC bit to 0. */
vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
vx_inl(chip, CDSP);
- snd_vx_delay(_chip, 10);
+ msleep(10);
/* Set the reset CODEC bit to 1. */
chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK;
vx_outl(chip, CDSP, chip->regCDSP);
vx_inl(chip, CDSP);
if (_chip->type == VX_TYPE_BOARD) {
- snd_vx_delay(_chip, 1);
+ msleep(1);
return;
}
- snd_vx_delay(_chip, 5); /* additionnel wait time for AKM's */
+ msleep(5); /* additionnel wait time for AKM's */
vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */
c = vx_inb(chip, CDSP);
if (c == CDSP_MAGIC)
return 0;
- snd_vx_delay(chip, 10);
+ msleep(10);
} while (time_after_eq(end_time, jiffies));
snd_printk(KERN_ERR "cannot find xilinx magic word (%x)\n", c);
return -EIO;
/* Set the reset CODEC bit to 1. */
vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_CODEC_RESET_MASK);
vx_inb(chip, CDSP);
- snd_vx_delay(_chip, 10);
+ msleep(10);
/* Set the reset CODEC bit to 0. */
chip->regCDSP &= ~VXP_CDSP_CODEC_RESET_MASK;
vx_outb(chip, CDSP, chip->regCDSP);
vx_inb(chip, CDSP);
- snd_vx_delay(_chip, 1);
+ msleep(1);
}
/*
vx_outb(chip, ICR, ICR_HF0);
/* TEMPO 250ms : wait until Xilinx is downloaded */
- snd_vx_delay(_chip, 300);
+ msleep(300);
/* test magical word */
if (vx_check_magic(_chip) < 0)
chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
vx_outb(chip, DIALOG, chip->regDIALOG);
vx_inb(chip, DIALOG);
- snd_vx_delay(_chip, 10);
+ msleep(10);
chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
vx_outb(chip, DIALOG, chip->regDIALOG);
vx_inb(chip, DIALOG);