*/
void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_control_bit_clr: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_control_bit_set: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
*/
uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
uint64_t ret = 0;
if (pcibus_info) {
default:
panic
("pcireg_tflush_get: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
*/
uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
uint64_t ret = 0;
if (pcibus_info) {
default:
panic
("pcireg_intr_status_get: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
return ret;
*/
void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_intr_enable_bit_clr: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_intr_enable_bit_set: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
uint64_t addr)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_intr_addr_addr_get: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
*/
void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_force_intr_set: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
*/
uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
uint64_t ret = 0;
if (pcibus_info) {
__sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]);
break;
default:
- panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", (void *)ptr);
+ panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", ptr);
}
}
void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
uint64_t val)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_int_ate_set: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
-uint64_t *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
+uint64_t __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
- uint64_t *ret = (uint64_t *) 0;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
+ uint64_t __iomem *ret = NULL;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_int_ate_addr: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
return ret;
uint64_t offset;
struct page *tmp;
struct tioca_common *tioca_common;
- struct tioca *ca_base;
+ struct tioca __iomem *ca_base;
tioca_common = tioca_kern->ca_common;
- ca_base = (struct tioca *)tioca_common->ca_common.bs_base;
+ ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
if (list_empty(tioca_kern->ca_devices))
return 0;
{
int cap_ptr;
uint32_t reg;
- struct tioca *tioca_base;
+ struct tioca __iomem *tioca_base;
struct pci_dev *pdev;
struct tioca_common *common;
* Set ca's fw to match
*/
- tioca_base = (struct tioca *)common->ca_common.bs_base;
+ tioca_base = (struct tioca __iomem*)common->ca_common.bs_base;
__sn_setq_relaxed(&tioca_base->ca_control1, CA_AGP_FW_ENABLE);
}
tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr)
{
struct tioca_common *tioca_common;
- struct tioca *ca_base;
+ struct tioca __iomem *ca_base;
uint64_t ct_addr;
dma_addr_t bus_addr;
uint32_t node_upper;
struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);
tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
- ca_base = (struct tioca *)tioca_common->ca_common.bs_base;
+ ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
ct_addr = PHYS_TO_TIODMA(paddr);
if (!ct_addr)