/*
* Limit the transfer speed to MW_DMA_2.
*/
- if (xfer_mode > XFER_MW_DMA_2)
- xfer_mode = XFER_MW_DMA_2;
+ xfer_mode = ide_rate_filter(drive, xfer_mode);
switch (xfer_mode) {
case XFER_MW_DMA_2:
{
int cyc = 0, dvs = 0, strobe = 0, hold = 0;
+ speed = ide_rate_filter(drive, speed);
+
if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
tune_cris_ide(drive, speed - XFER_PIO_0);
return ide_config_drive_speed(drive, speed);
int mem_sttime;
int mem_stcfg;
+ speed = ide_rate_filter(drive, speed);
+
mem_sttime = 0;
mem_stcfg = au_readl(MEM_STCFG2);
struct ide_timing t, p;
int T, UT;
+ speed = ide_rate_filter(drive, speed);
+
if (speed != XFER_PIO_SLOW)
ide_config_drive_speed(drive, speed);
struct ide_timing t, p;
unsigned int T, UT;
+ speed = ide_rate_filter(drive, speed);
+
if (speed != XFER_PIO_SLOW)
ide_config_drive_speed(drive, speed);
pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
u32 *timings, *timings2;
+ speed = ide_rate_filter(drive, speed);
+
if (pmif == NULL)
return 1;
switch(speed) {
#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
case XFER_UDMA_6:
- if (pmif->kind != controller_sh_ata6)
- return 1;
case XFER_UDMA_5:
- if (pmif->kind != controller_un_ata6 &&
- pmif->kind != controller_k2_ata6 &&
- pmif->kind != controller_sh_ata6)
- return 1;
case XFER_UDMA_4:
case XFER_UDMA_3:
- if (drive->hwif->cbl != ATA_CBL_PATA80)
- return 1;
case XFER_UDMA_2:
case XFER_UDMA_1:
case XFER_UDMA_0: