Do the timer interrupt only once on CPU 0 ...

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index 6f87f52d482bd949c73b00e83ae0b29b925e8672..511c89d65f3821371ac34a59f4362e830f45f6e5 100644 (file)
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -107,17 +107,18 @@ void sb1250_timer_interrupt(struct pt_regs *regs)
        ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
                       IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
 
-       /*
-        * CPU 0 handles the global timer interrupt job
-        */
        if (cpu == 0) {
+               /*
+                * CPU 0 handles the global timer interrupt job
+                */
                ll_timer_interrupt(irq, regs);
        }
-
-       /*
-        * every CPU should do profiling and process accouting
-        */
-       ll_local_timer_interrupt(irq, regs);
+       else {
+               /*
+                * other CPUs should just do profiling and process accounting
+                */
+               ll_local_timer_interrupt(irq, regs);
+       }
 }
 
 /*