[ARM] 3252/1: help gcc do the best with ___arch__swab32

Patch from Nicolas Pitre

Depending on your gcc version, the current C-only implementation would
produce suboptimal code, ranging from a bad register selection forcing
an additional mov instruction to a failure to merge the eor and the ror
in a single instruction.  With a little help gcc always produces the
best code.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/include/asm-arm/byteorder.h b/include/asm-arm/byteorder.h
index 741f5bc5d016ea5888eb95290d909fc2c027a32f..17eaf8bdf0925a7b0146df2d6e35f8ac08cf3484 100644 (file)
--- a/include/asm-arm/byteorder.h
+++ b/include/asm-arm/byteorder.h
@@ -22,7 +22,16 @@ static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
 {
        __u32 t;
 
-       t = x ^ ((x << 16) | (x >> 16));        /* eor r1,r0,r0,ror #16  */
+       if (__builtin_constant_p(x)) {
+               t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */
+       } else {
+               /*
+                * The compiler needs a bit of a hint here to always do the
+                * right thing and not screw it up to different degrees
+                * depending on the gcc version.
+                */
+               asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x));
+       }
        x = (x << 24) | (x >> 8);               /* mov r0,r0,ror #8      */
        t &= ~0x00FF0000;                       /* bic r1,r1,#0x00FF0000 */
        x ^= (t >> 8);                          /* eor r0,r0,r1,lsr #8   */