are also not changed, and the Bootloader does 100% of the hardware
configuration.
+config MEM_SIZE
+ int "SDRAM Memory Size in MBytes"
+ depends on BFIN_KERNEL_CLOCK
+ default 64
+
config MEM_ADD_WIDTH
int "Memory Address Width"
depends on BFIN_KERNEL_CLOCK
This can be between 1 and 15
System Clock = (PLL frequency) / (this setting)
+config MAX_MEM_SIZE
+ int "Max SDRAM Memory Size in MBytes"
+ depends on !BFIN_KERNEL_CLOCK && !MPU
+ default 512
+ help
+ This is the max memory size that the kernel will create CPLB
+ tables for. Your system will not be able to handle any more.
+
#
# Max & Min Speeds for various Chips
#
comment "Memory Setup"
-config MEM_SIZE
- int "SDRAM Memory Size in MBytes"
- default 32 if BFIN533_EZKIT
- default 64 if BFIN527_EZKIT
- default 64 if BFIN537_STAMP
- default 64 if BFIN548_EZKIT
- default 64 if BFIN561_EZKIT
- default 128 if BFIN533_STAMP
- default 64 if PNAV10
- default 32 if H8606_HVSISTEMAS
- default 64 if BFIN548_BLUETECHNIX_CM
- default 64 if BFIN532_IP0X
-
choice
prompt "DDR SDRAM Chip Type"
depends on (BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
#include <asm/cplb.h>
#include <asm/cplbinit.h>
+#ifdef CONFIG_MAX_MEM_SIZE
+# define CPLB_MEM CONFIG_MAX_MEM_SIZE
+#else
+# define CPLB_MEM CONFIG_MEM_SIZE
+#endif
+
/*
* Number of required data CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
* 1 for ASYNC Memory
*/
-#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \
+#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
+ ASYNC_MEMORY_CPLB_COVERAGE) * 2)
/*
* possibly 1 for L2 Instruction Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
*/
-#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
+#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
u_long icplb_table[MAX_CPLBS + 1];
BOOTMEM_DEFAULT);
}
+#define EBSZ_TO_MEG(ebsz) \
+({ \
+ int meg = 0; \
+ switch (ebsz & 0xf) { \
+ case 0x1: meg = 16; break; \
+ case 0x3: meg = 32; break; \
+ case 0x5: meg = 64; break; \
+ case 0x7: meg = 128; break; \
+ case 0x9: meg = 256; break; \
+ case 0xb: meg = 512; break; \
+ } \
+ meg; \
+})
+static inline int __init get_mem_size(void)
+{
+#ifdef CONFIG_MEM_SIZE
+ return CONFIG_MEM_SIZE;
+#else
+# if defined(EBIU_SDBCTL)
+# if defined(BF561_FAMILY)
+ int ret = 0;
+ u32 sdbctl = bfin_read_EBIU_SDBCTL();
+ ret += EBSZ_TO_MEG(sdbctl >> 0);
+ ret += EBSZ_TO_MEG(sdbctl >> 8);
+ ret += EBSZ_TO_MEG(sdbctl >> 16);
+ ret += EBSZ_TO_MEG(sdbctl >> 24);
+ return ret;
+# else
+ return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
+# endif
+# elif defined(EBIU_DDRCTL1)
+ switch (bfin_read_EBIU_DDRCTL1() & 0xc0000) {
+ case DEVSZ_64: return 64;
+ case DEVSZ_128: return 128;
+ case DEVSZ_256: return 256;
+ case DEVSZ_512: return 512;
+ default: return 0;
+ }
+# endif
+#endif
+ BUG();
+}
+
void __init setup_arch(char **cmdline_p)
{
unsigned long sclk, cclk;
/* setup memory defaults from the user config */
physical_mem_end = 0;
- _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
+ _ramend = get_mem_size() * 1024 * 1024;
memset(&bfin_memmap, 0, sizeof(bfin_memmap));
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
+#ifdef CONFIG_MEM_SIZE
#if (CONFIG_MEM_SIZE % 4)
#error "SDRAM mem size must be multible of 4MB"
#endif
-
+#endif