[ARM] 4657/1: AT91: Header definition update

Add definitions of registers / bits found on some AT91SAM9 processors

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index 33ff5b6798ee4b46a60881efad670ac8b2645e7f..34804eaab4f26752373aa602b2e10f05554a480b 100644 (file)
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -37,7 +37,9 @@
 #define        AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
 #define        AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
 
-#define        AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register */
+#define        AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [SAM9RL only] */
+
+#define        AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
 #define                AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
 #define                AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [AT91SAM926x only] */
 #define                AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */

diff --git a/include/asm-arm/arch-at91/at91_twi.h b/include/asm-arm/arch-at91/at91_twi.h
index ca9a90733456be5fba159820216bc4fd21f04187..f9f2e3cd95c5766caed7ccb2772c930b8885ac61 100644 (file)
--- a/include/asm-arm/arch-at91/at91_twi.h
+++ b/include/asm-arm/arch-at91/at91_twi.h
@@ -21,6 +21,8 @@
 #define                AT91_TWI_STOP           (1 <<  1)       /* Send a Stop Condition */
 #define                AT91_TWI_MSEN           (1 <<  2)       /* Master Transfer Enable */
 #define                AT91_TWI_MSDIS          (1 <<  3)       /* Master Transfer Disable */
+#define                AT91_TWI_SVEN           (1 <<  4)       /* Slave Transfer Enable [SAM9260 only] */
+#define                AT91_TWI_SVDIS          (1 <<  5)       /* Slave Transfer Disable [SAM9260 only] */
 #define                AT91_TWI_SWRST          (1 <<  7)       /* Software Reset */
 
 #define        AT91_TWI_MMR            0x04            /* Master Mode Register */
@@ -32,6 +34,9 @@
 #define                AT91_TWI_MREAD          (1    << 12)    /* Master Read Direction */
 #define                AT91_TWI_DADR           (0x7f << 16)    /* Device Address */
 
+#define        AT91_TWI_SMR            0x08            /* Slave Mode Register [SAM9260 only] */
+#define                AT91_TWI_SADR           (0x7f << 16)    /* Slave Address */
+
 #define        AT91_TWI_IADR           0x0c            /* Internal Address Register */
 
 #define        AT91_TWI_CWGR           0x10            /* Clock Waveform Generator Register */
@@ -43,9 +48,15 @@
 #define                AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
 #define                AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
 #define                AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
+#define                AT91_TWI_SVREAD         (1 <<  3)       /* Slave Read [SAM9260 only] */
+#define                AT91_TWI_SVACC          (1 <<  4)       /* Slave Access [SAM9260 only] */
+#define                AT91_TWI_GACC           (1 <<  5)       /* General Call Access [SAM9260 only] */
 #define                AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error [AT91RM9200 only] */
 #define                AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error [AT91RM9200 only] */
 #define                AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
+#define                AT91_TWI_ARBLST         (1 <<  9)       /* Arbitration Lost [SAM9260 only] */
+#define                AT91_TWI_SCLWS          (1 << 10)       /* Clock Wait State [SAM9260 only] */
+#define                AT91_TWI_EOSACC         (1 << 11)       /* End of Slave Address [SAM9260 only] */
 
 #define        AT91_TWI_IER            0x24            /* Interrupt Enable Register */
 #define        AT91_TWI_IDR            0x28            /* Interrupt Disable Register */

diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h
index aacb1e9764220d484be05a0db74a3251d0ad1f76..a8e9fec6c7352ad5ff7441d3f0aa315df42ae689 100644 (file)
--- a/include/asm-arm/arch-at91/at91sam9260_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9260_matrix.h
@@ -67,7 +67,7 @@
 #define                AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
 #define                        AT91_MATRIX_CS4A_SMC            (0 << 4)
 #define                        AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
-#define                AT91_MATRIX_CS5A                (1 << 5 )       /* Chip Select 5 Assignment */
+#define                AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
 #define                        AT91_MATRIX_CS5A_SMC            (0 << 5)
 #define                        AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
 #define                AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */