[ARM] Fix SA110/SA1100 cache flushing

We had two implementations for flushing the cache, which meant StrongARM
caches weren't being correctly flushed.  Fix this by always using the
v4wb_flush_kern_cache_all method, rather than duplicating it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 5c4055b62d976808a9660903393d501dce5a5599..54e3c5bb5186a88203ed83441e58926347cb55a5 100644 (file)
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -10,7 +10,7 @@
 #include <linux/config.h>
 #include <linux/linkage.h>
 #include <linux/init.h>
-#include <asm/hardware.h>
+#include <asm/memory.h>
 #include <asm/page.h>
 #include "proc-macros.S"
 
@@ -46,6 +46,11 @@
  */
 #define CACHE_DLIMIT   (CACHE_DSIZE * 4)
 
+       .data
+flush_base:
+       .long   FLUSH_BASE
+       .text
+
 /*
  *     flush_user_cache_all()
  *
@@ -63,11 +68,21 @@ ENTRY(v4wb_flush_kern_cache_all)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
 __flush_whole_cache:
-       mov     r0, #FLUSH_BASE
-       add     r1, r0, #CACHE_DSIZE
-1:     ldr     r2, [r0], #32
-       cmp     r0, r1
+       ldr     r3, =flush_base
+       ldr     r1, [r3, #0]
+       eor     r1, r1, #CACHE_DSIZE
+       str     r1, [r3, #0]
+       add     r2, r1, #CACHE_DSIZE
+1:     ldr     r3, [r1], #32
+       cmp     r1, r2
+       blo     1b
+#ifdef FLUSH_BASE_MINICACHE
+       add     r2, r2, #FLUSH_BASE_MINICACHE - FLUSH_BASE
+       sub     r1, r2, #512                    @ only 512 bytes
+1:     ldr     r3, [r1], #32
+       cmp     r1, r2
        blo     1b
+#endif
        mcr     p15, 0, ip, c7, c10, 4          @ drain write buffer
        mov     pc, lr
 
@@ -82,6 +97,7 @@ __flush_whole_cache:
  *     - flags - vma_area_struct flags describing address space
  */
 ENTRY(v4wb_flush_user_cache_range)
+       mov     ip, #0
        sub     r3, r1, r0                      @ calculate total size
        tst     r2, #VM_EXEC                    @ executable region?
        mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache

diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index c916a6cae40428e53ade79211ba8994e70583cd4..a2dd5ae1077dda0c5257a768a6d69c880c0781af 100644 (file)
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -26,22 +26,7 @@
  * the cache line size of the I and D cache
  */
 #define DCACHELINESIZE 32
-#define FLUSH_OFFSET   32768
 
-       .macro flush_110_dcache rd, ra, re
-       ldr     \rd, =flush_base
-       ldr     \ra, [\rd]
-       eor     \ra, \ra, #FLUSH_OFFSET
-       str     \ra, [\rd]
-       add     \re, \ra, #16384                @ only necessary for 16k
-1001:  ldr     \rd, [\ra], #DCACHELINESIZE
-       teq     \re, \ra
-       bne     1001b
-       .endm
-
-       .data
-flush_base:
-       .long   FLUSH_BASE
        .text
 
 /*
@@ -145,13 +130,11 @@ ENTRY(cpu_sa110_dcache_clean_area)
  */
        .align  5
 ENTRY(cpu_sa110_switch_mm)
-       flush_110_dcache        r3, ip, r1
-       mov     r1, #0
-       mcr     p15, 0, r1, c7, c5, 0           @ invalidate I cache
-       mcr     p15, 0, r1, c7, c10, 4          @ drain WB
+       str     lr, [sp, #-4]!
+       bl      v4wb_flush_kern_cache_all       @ clears IP
        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
-       mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
-       mov     pc, lr
+       mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
+       ldr     pc, [sp], #4
 
 /*
  * cpu_sa110_set_pte(ptep, pte)

diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 41f21f2dd8ffae766afeae26f641a75a1994d6f2..777ad99c14395584690dfc32cd3c297540edca16 100644 (file)
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -30,30 +30,6 @@
  * the cache line size of the I and D cache
  */
 #define DCACHELINESIZE 32
-#define FLUSH_OFFSET   32768
-
-       .macro flush_1100_dcache rd, ra, re
-       ldr     \rd, =flush_base
-       ldr     \ra, [\rd]
-       eor     \ra, \ra, #FLUSH_OFFSET
-       str     \ra, [\rd]
-       add     \re, \ra, #8192                 @ only necessary for 8k
-1001:  ldr     \rd, [\ra], #DCACHELINESIZE
-       teq     \re, \ra
-       bne     1001b
-#ifdef FLUSH_BASE_MINICACHE
-       add     \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE
-       add     \re, \ra, #512                  @ only 512 bytes
-1002:  ldr     \rd, [\ra], #DCACHELINESIZE
-       teq     \re, \ra
-       bne     1002b
-#endif
-       .endm
-
-       .data
-flush_base:
-       .long   FLUSH_BASE
-       .text
 
        __INIT
 
@@ -79,9 +55,8 @@ ENTRY(cpu_sa1100_proc_fin)
        stmfd   sp!, {lr}
        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
        msr     cpsr_c, ip
-       flush_1100_dcache r0, r1, r2            @ clean caches
-       mov     r0, #0
-       mcr     p15, 0, r0, c15, c2, 2          @ Disable clock switching
+       bl      v4wb_flush_kern_cache_all
+       mcr     p15, 0, ip, c15, c2, 2          @ Disable clock switching
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
@@ -167,14 +142,12 @@ ENTRY(cpu_sa1100_dcache_clean_area)
  */
        .align  5
 ENTRY(cpu_sa1100_switch_mm)
-       flush_1100_dcache r3, ip, r1
-       mov     ip, #0
-       mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
+       str     lr, [sp, #-4]!
+       bl      v4wb_flush_kern_cache_all       @ clears IP
        mcr     p15, 0, ip, c9, c0, 0           @ invalidate RB
-       mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
-       mov     pc, lr
+       ldr     pc, [sp], #4
 
 /*
  * cpu_sa1100_set_pte(ptep, pte)