[ARM] 4453/1: Fully Decode ARM instruction set state in show_regs() tombstone

The ARM show_regs() tombstone only partially decodes which ARM ISA was
executing at the time a fault occurred displaying either "(T)" for the
Thumb case or nothing at all for other cases.  This patch therefore
explicitly identifies which state the processor is in at the time of
a fault: ARM, Thumb, Jazelle or JazelleEE.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 842361777d4e63782a96535c6c50cfbf3faedd19..93b7f8e22dcc1b3b69aa424c60d0a91bed19f772 100644 (file)
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -44,6 +44,10 @@ static const char *processor_modes[] = {
   "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32"
 };
 
+static const char *isa_modes[] = {
+  "ARM" , "Thumb" , "Jazelle", "ThumbEE"
+};
+
 extern void setup_mm_for_reboot(char mode);
 
 static volatile int hlt_counter;
@@ -230,11 +234,11 @@ void __show_regs(struct pt_regs *regs)
        buf[3] = flags & PSR_V_BIT ? 'V' : 'v';
        buf[4] = '\0';
 
-       printk("Flags: %s  IRQs o%s  FIQs o%s  Mode %s%s  Segment %s\n",
+       printk("Flags: %s  IRQs o%s  FIQs o%s  Mode %s  ISA %s  Segment %s\n",
                buf, interrupts_enabled(regs) ? "n" : "ff",
                fast_interrupts_enabled(regs) ? "n" : "ff",
                processor_modes[processor_mode(regs)],
-               thumb_mode(regs) ? " (T)" : "",
+               isa_modes[isa_mode(regs)],
                get_fs() == get_ds() ? "kernel" : "user");
 #ifdef CONFIG_CPU_CP15
        {

diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h
index ee3d93c281d809900cd13086932755a368f18e40..ff038b65f3709e3867aa8565705b16fd5bcf6ba3 100644 (file)
--- a/include/asm-arm/ptrace.h
+++ b/include/asm-arm/ptrace.h
@@ -103,6 +103,10 @@ struct pt_regs {
 #define thumb_mode(regs) (0)
 #endif
 
+#define isa_mode(regs) \
+       ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
+        (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
+
 #define processor_mode(regs) \
        ((regs)->ARM_cpsr & MODE_MASK)