int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
{
dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
- __FUNCTION__, dma_addr, size);
+ __func__, dma_addr, size);
return (dev->bus == &pci_bus_type) &&
((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
}
*/
int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
{
- dev_dbg(&dev->dev, "%s: %llx\n", __FUNCTION__, mask);
+ dev_dbg(&dev->dev, "%s: %llx\n", __func__, mask);
if (mask >= PHYS_OFFSET + SZ_64M - 1)
return 0;
int
pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
{
- dev_dbg(&dev->dev, "%s: %llx\n", __FUNCTION__, mask);
+ dev_dbg(&dev->dev, "%s: %llx\n", __func__, mask);
if (mask >= PHYS_OFFSET + SZ_64M - 1)
return 0;
h720x_gpio_handler(unsigned int mask, unsigned int irq,
struct irq_desc *desc)
{
- IRQDBG("%s irq: %d\n",__FUNCTION__,irq);
+ IRQDBG("%s irq: %d\n", __func__, irq);
desc = irq_desc + irq;
while (mask) {
if (mask & 1) {
mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOA(0);
- IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
+ IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
h720x_gpio_handler(mask, irq, desc);
}
unsigned int mask, irq;
mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOB(0);
- IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
+ IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
h720x_gpio_handler(mask, irq, desc);
}
mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOC(0);
- IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
+ IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
h720x_gpio_handler(mask, irq, desc);
}
mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOD(0);
- IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
+ IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
h720x_gpio_handler(mask, irq, desc);
}
mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOE(0);
- IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
+ IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
h720x_gpio_handler(mask, irq, desc);
}
#endif
if (!imxdma->name) {
printk(KERN_CRIT "%s: called for not allocated channel %d\n",
- __FUNCTION__, dma_ch);
+ __func__, dma_ch);
return 0;
}
if (!imxdma->name) {
printk(KERN_CRIT "%s: called for not allocated channel %d\n",
- __FUNCTION__, dma_ch);
+ __func__, dma_ch);
return -ENODEV;
}
if (!imxdma->name) {
printk(KERN_CRIT "%s: called for not allocated channel %d\n",
- __FUNCTION__, dma_ch);
+ __func__, dma_ch);
return;
}
if (dma_ch >= IMX_DMA_CHANNELS) {
printk(KERN_CRIT "%s: called for non-existed channel %d\n",
- __FUNCTION__, dma_ch);
+ __func__, dma_ch);
return -EINVAL;
}
if (!imxdma->name) {
printk(KERN_CRIT
"%s: trying to free channel %d which is already freed\n",
- __FUNCTION__, dma_ch);
+ __func__, dma_ch);
return;
}
}
}
- printk(KERN_ERR "%s: no free DMA channel found\n", __FUNCTION__);
+ printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
return -ENODEV;
}
static void
imx_gpio_ack_irq(unsigned int irq)
{
- DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
+ DEBUG_IRQ("%s: irq %d\n", __func__, irq);
ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
}
static void
imx_gpio_mask_irq(unsigned int irq)
{
- DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
+ DEBUG_IRQ("%s: irq %d\n", __func__, irq);
IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32));
}
static void
imx_gpio_unmask_irq(unsigned int irq)
{
- DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
+ DEBUG_IRQ("%s: irq %d\n", __func__, irq);
IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32);
}
static void __init iq81340mc_timer_init(void)
{
unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
- printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq);
+ printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq);
iop_init_time(bus_freq);
}
static void __init iq81340sc_timer_init(void)
{
unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
- printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq);
+ printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq);
iop_init_time(bus_freq);
}
, 0, iop13xx_atux_mem_size, MT_DEVICE);
if (!iop13xx_atux_mem_base) {
printk("%s: atux allocation "
- "failed\n", __FUNCTION__);
+ "failed\n", __func__);
BUG();
}
} else
iop13xx_atux_mem_size = 0;
PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
- __FUNCTION__, atu, iop13xx_atux_mem_size,
+ __func__, atu, iop13xx_atux_mem_size,
iop13xx_atux_mem_base);
break;
case 1:
, 0, iop13xx_atue_mem_size, MT_DEVICE);
if (!iop13xx_atue_mem_base) {
printk("%s: atue allocation "
- "failed\n", __FUNCTION__);
+ "failed\n", __func__);
BUG();
}
} else
iop13xx_atue_mem_size = 0;
PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
- __FUNCTION__, atu, iop13xx_atue_mem_size,
+ __func__, atu, iop13xx_atue_mem_size,
iop13xx_atue_mem_base);
break;
}
if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
iop13xx_devices[plat_idx++] = &iq8134x_flash;
else
- printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__);
+ printk(KERN_ERR "%s: Failed to probe flash size\n", __func__);
#endif
platform_add_devices(iop13xx_devices, plat_idx);
if (isr & PCI_ISR_PFE) {
/* make sure the Master Abort bit is reset */
*PCI_ISR = PCI_ISR_PFE;
- pr_debug("%s failed\n", __FUNCTION__);
+ pr_debug("%s failed\n", __func__);
return 1;
}
else
rc = gtwx5715_irqmap[slot][pin-1];
- printk("%s: Mapped slot %d pin %d to IRQ %d\n", __FUNCTION__,slot, pin, rc);
+ printk("%s: Mapped slot %d pin %d to IRQ %d\n", __func__, slot, pin, rc);
return(rc);
}
val &= ~((1 << 24) << irq);
writel(val, NETX_DPMAS_INT_EN);
- DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq);
+ DEBUG_IRQ("%s: irq %d\n", __func__, _irq);
}
static void
val = readl(NETX_DPMAS_INT_EN);
val &= ~((1 << 24) << irq);
writel(val, NETX_DPMAS_INT_EN);
- DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq);
+ DEBUG_IRQ("%s: irq %d\n", __func__, _irq);
}
static void
val = readl(NETX_DPMAS_INT_EN);
val |= (1 << 24) << irq;
writel(val, NETX_DPMAS_INT_EN);
- DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq);
+ DEBUG_IRQ("%s: irq %d\n", __func__, _irq);
}
static struct irq_chip netx_hif_chip = {
unsigned long flags;
if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
- pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
+ pr_debug("%s: invalid GPIO %d\n", __func__, pin);
return -EINVAL;
}
int mask;
if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
- pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
+ pr_debug("%s: invalid GPIO %d\n", __func__, pin);
return -EINVAL;
}
unsigned long flags;
if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
- pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
+ pr_debug("%s: invalid GPIO %d\n", __func__, pin);
return -EINVAL;
}
if (gpio_label[pin]) {
pr_debug("%s: GPIO %d already used as %s\n",
- __FUNCTION__, pin, gpio_label[pin]);
+ __func__, pin, gpio_label[pin]);
ret = -EBUSY;
} else
gpio_label[pin] = label ? label : "?";
void gpio_free(unsigned pin)
{
if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
- pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
+ pr_debug("%s: invalid GPIO %d\n", __func__, pin);
return;
}
if (!gpio_label[pin])
- pr_warning("%s: GPIO %d already freed\n", __FUNCTION__, pin);
+ pr_warning("%s: GPIO %d already freed\n", __func__, pin);
else
gpio_label[pin] = NULL;
}
(*clkp)->set_parent((*clkp), (*clkp)->parent);
}
pr_debug("%s: clock %s, rate %ld\n",
- __FUNCTION__, (*clkp)->name, (*clkp)->rate);
+ __func__, (*clkp)->name, (*clkp)->rate);
}
local_clk_use(&ck_pll4);
if (!dma_channels[ch].name) {
printk(KERN_CRIT
"%s: trying to free channel %d which is already freed\n",
- __FUNCTION__, ch);
+ __func__, ch);
return;
}
{
int irq;
- dev_dbg(&dev->dev, "%s: slot=%x, pin=%x\n", __FUNCTION__, slot, pin);
+ dev_dbg(&dev->dev, "%s: slot=%x, pin=%x\n", __func__, slot, pin);
irq = it8152_pci_map_irq(dev, slot, pin);
if (irq)
struct pxamci_platform_data *p_d = dev->platform_data;
if ((1 << vdd) & p_d->ocr_mask) {
- printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
+ printk(KERN_DEBUG "%s: on\n", __func__);
GPCR(105) = GPIO_bit(105);
} else {
GPSR(105) = GPIO_bit(105);
- printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
+ printk(KERN_DEBUG "%s: off\n", __func__);
}
}
if (!dma_channels[dma_ch].name) {
printk (KERN_CRIT
"%s: trying to free channel %d which is already freed\n",
- __FUNCTION__, dma_ch);
+ __func__, dma_ch);
return;
}
"MMC card detect", data);
if (err) {
printk(KERN_ERR "%s: can't request MMC card detect IRQ: %d\n",
- __FUNCTION__, err);
+ __func__, err);
return err;
}
struct pxamci_platform_data* p_d = dev->platform_data;
if (( 1 << vdd) & p_d->ocr_mask) {
- printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
+ printk(KERN_DEBUG "%s: on\n", __func__);
MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
} else {
- printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
+ printk(KERN_DEBUG "%s: off\n", __func__);
MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
}
}
ConXS_BCR = trizeps_conxs_bcr;
}
- pr_debug("%s: o%s 0x%x\n", __FUNCTION__, power ? "n": "ff", trizeps_conxs_bcr);
+ pr_debug("%s: o%s 0x%x\n", __func__, power ? "n": "ff", trizeps_conxs_bcr);
}
/* backlight power switching for LCD panel */
} else {
trizeps_conxs_bcr &= ~ConXS_BCR_L_DISP;
}
- pr_debug("%s: o%s 0x%x\n", __FUNCTION__, on ? "n" : "ff", trizeps_conxs_bcr);
+ pr_debug("%s: o%s 0x%x\n", __func__, on ? "n" : "ff", trizeps_conxs_bcr);
ConXS_BCR = trizeps_conxs_bcr;
}
struct pxamci_platform_data* p_d = dev->platform_data;
if (( 1 << vdd) & p_d->ocr_mask) {
- pr_debug("%s: on\n", __FUNCTION__);
+ pr_debug("%s: on\n", __func__);
/* FIXME fill in values here */
} else {
- pr_debug("%s: off\n", __FUNCTION__);
+ pr_debug("%s: off\n", __func__);
/* FIXME fill in values here */
}
}
if (ret < 0)
printk(KERN_ERR
"%s: SA-1111 initialization failed (%d)\n",
- __FUNCTION__, ret);
+ __func__, ret);
/* maybe turn on 5v0 from the start */
/* detect on->off and off->on transitions */
if ((!old_5V_bitmap) && (badge4_5V_bitmap)) {
/* was off, now on */
- printk(KERN_INFO "%s: enabling 5V supply rail\n", __FUNCTION__);
+ printk(KERN_INFO "%s: enabling 5V supply rail\n", __func__);
GPSR = BADGE4_GPIO_PCMEN5V;
} else if ((old_5V_bitmap) && (!badge4_5V_bitmap)) {
/* was on, now off */
- printk(KERN_INFO "%s: disabling 5V supply rail\n", __FUNCTION__);
+ printk(KERN_INFO "%s: disabling 5V supply rail\n", __func__);
GPCR = BADGE4_GPIO_PCMEN5V;
}
if (settings->speed == 0) {
panic("%s: couldn't find dram setting for speed %d\n",
- __FUNCTION__, new_speed);
+ __func__, new_speed);
}
/* No risk, no fun: run with interrupts on! */
if (err) {
printk(KERN_ERR
"%s: unable to request IRQ %d for %s\n",
- __FUNCTION__, IRQ_DMA0 + i, device_id);
+ __func__, IRQ_DMA0 + i, device_id);
dma->device = 0;
return err;
}
if (regs == (dma_regs_t *)&DDAR(i))
break;
if (i >= SA1100_DMA_CHANNELS) {
- printk(KERN_ERR "%s: bad DMA identifier\n", __FUNCTION__);
+ printk(KERN_ERR "%s: bad DMA identifier\n", __func__);
return;
}
if (!dma_chan[i].device) {
- printk(KERN_ERR "%s: Trying to free free DMA\n", __FUNCTION__);
+ printk(KERN_ERR "%s: Trying to free free DMA\n", __func__);
return;
}
if (regs == (dma_regs_t *)&DDAR(i))
break;
if (i >= SA1100_DMA_CHANNELS) {
- printk(KERN_ERR "%s: bad DMA identifier\n", __FUNCTION__);
+ printk(KERN_ERR "%s: bad DMA identifier\n", __func__);
return;
}
case IPAQ_EGPIO_CODEC_NRESET:
case IPAQ_EGPIO_AUDIO_ON:
case IPAQ_EGPIO_QMUTE:
- printk("%s: error - should not be called\n", __FUNCTION__);
+ printk("%s: error - should not be called\n", __func__);
break;
case IPAQ_EGPIO_OPT_NVRAM_ON:
SET_ASIC2(GPIO2_OPT_ON_NVRAM);
static u16 asic2_data;
int result = 0;
- printk("%s %d\n", __FUNCTION__, req);
+ printk("%s %d\n", __func__, req);
switch (req) {
case PM_RESUME:
asic2_data = H3800_ASIC2_GPIOPIOD;
break;
default:
- printk("%s: unrecognized PM callback\n", __FUNCTION__);
+ printk("%s: unrecognized PM callback\n", __func__);
break;
}
return result;
{
int i;
- if (0) printk("%s: interrupt received\n", __FUNCTION__);
+ if (0) printk("%s: interrupt received\n", __func__);
desc->chip->ack(irq);
/* KPIO */
irq = H3800_ASIC2_KPIINTFLAG;
- if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq);
+ if (0) printk("%s KPIO 0x%08X\n", __func__, irq);
for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++)
if (irq & kpio_irq_mask[j])
handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j);
/* GPIO2 */
irq = H3800_ASIC2_GPIINTFLAG;
- if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq);
+ if (0) printk("%s GPIO 0x%08X\n", __func__, irq);
for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++)
if (irq & gpio_irq_mask[j])
handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j);
}
if (i >= MAX_ASIC_ISR_LOOPS)
- printk("%s: interrupt processing overrun\n", __FUNCTION__);
+ printk("%s: interrupt processing overrun\n", __func__);
/* For level-based interrupts */
desc->chip->unmask(irq);
default:
printk(KERN_DEBUG "\"%s\" malformed at "
"character: \'%c\'",
- __FUNCTION__,
+ __func__,
*str);
*(str + 1) = '\0';
}
static inline void omap_enable_channel_irq(int lch);
#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
- __FUNCTION__);
+ __func__);
#ifdef CONFIG_ARCH_OMAP15XX
/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
u32 reg;
if (!cpu_class_is_omap2()) {
- printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __FUNCTION__);
+ printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
return;
}
if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
spin_unlock_irqrestore(&dm_timer_lock, flags);
printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
- __FILE__, __LINE__, __FUNCTION__, id);
+ __FILE__, __LINE__, __func__, id);
dump_stack();
return NULL;
}
dmadbg_dumpregs(fname, line, chan, &state);
}
-#define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan))
-#define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan))
+#define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
+#define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
#else
#define dbg_showregs(chan) do { } while(0)
#define dbg_showchan(chan) do { } while(0)
if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
pr_debug("%s: buff not yet loaded, no more todo\n",
- __FUNCTION__);
+ __func__);
} else {
chan->load_state = S3C2410_DMALOAD_1RUNNING;
s3c2410_dma_loadbuffer(chan, chan->next);
return -EINVAL;
pr_debug("%s: id=%p, data=%08x, size=%d\n",
- __FUNCTION__, id, (unsigned int)data, size);
+ __func__, id, (unsigned int)data, size);
buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
if (buf == NULL) {
pr_debug("%s: out of memory (%ld alloc)\n",
- __FUNCTION__, (long)sizeof(*buf));
+ __func__, (long)sizeof(*buf));
return -ENOMEM;
}
- //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
+ //pr_debug("%s: new buffer %p\n", __func__, buf);
//dbg_showchan(chan);
buf->next = NULL;
if (chan->curr == NULL) {
/* we've got nothing loaded... */
pr_debug("%s: buffer %p queued onto empty channel\n",
- __FUNCTION__, buf);
+ __func__, buf);
chan->curr = buf;
chan->end = buf;
chan->next = NULL;
} else {
pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
- chan->number, __FUNCTION__, buf);
+ chan->number, __func__, buf);
if (chan->end == NULL)
pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
- chan->number, __FUNCTION__, chan);
+ chan->number, __func__, chan);
chan->end->next = buf;
chan->end = buf;
if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
/* flag error? */
printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
- chan->number, __FUNCTION__);
+ chan->number, __func__);
return;
}
break;
if (buf->magic != BUF_MAGIC) {
printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
- chan->number, __FUNCTION__, buf);
+ chan->number, __func__, buf);
return IRQ_HANDLED;
}
if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
/* flag error? */
printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
- chan->number, __FUNCTION__);
+ chan->number, __func__);
return IRQ_HANDLED;
}
if (!chan->irq_claimed) {
pr_debug("dma%d: %s : requesting irq %d\n",
- channel, __FUNCTION__, chan->irq);
+ channel, __func__, chan->irq);
chan->irq_claimed = 1;
local_irq_restore(flags);
/* need to setup */
- pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan);
+ pr_debug("%s: channel initialised, %p\n", __func__, chan);
return chan->number | DMACH_LOW_LEVEL;
}
if (chan->state != S3C2410_DMA_IDLE) {
pr_debug("%s: need to stop dma channel %p\n",
- __FUNCTION__, chan);
+ __func__, chan);
/* possibly flush the channel */
s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
unsigned long flags;
unsigned long tmp;
- pr_debug("%s:\n", __FUNCTION__);
+ pr_debug("%s:\n", __func__);
dbg_showchan(chan);
struct s3c2410_dma_buf *buf, *next;
unsigned long flags;
- pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number);
+ pr_debug("%s: chan %p (%d)\n", __func__, chan, chan->number);
dbg_showchan(chan);
local_irq_save(flags);
if (chan->state != S3C2410_DMA_IDLE) {
- pr_debug("%s: stopping channel...\n", __FUNCTION__ );
+ pr_debug("%s: stopping channel...\n", __func__ );
s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
}
next = buf->next;
pr_debug("%s: free buffer %p, next %p\n",
- __FUNCTION__, buf, buf->next);
+ __func__, buf, buf->next);
s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
s3c2410_dma_freebuf(buf);
if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
pr_debug("%s: buff not yet loaded, no more todo\n",
- __FUNCTION__);
+ __func__);
} else {
chan->load_state = S3C2410_DMALOAD_1RUNNING;
s3c2410_dma_loadbuffer(chan, chan->next);
struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
- __FUNCTION__, channel, xferunit, dcon);
+ __func__, channel, xferunit, dcon);
if (chan == NULL)
return -EINVAL;
- pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon);
+ pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
dcon |= chan->dcon & dma_sel.dcon_mask;
- pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon);
+ pr_debug("%s: New dcon is %08x\n", __func__, dcon);
switch (xferunit) {
case 1:
break;
default:
- pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit);
+ pr_debug("%s: bad transfer size %d\n", __func__, xferunit);
return -EINVAL;
}
dcon |= S3C2410_DCON_HWTRIG;
dcon |= S3C2410_DCON_INTREQ;
- pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon);
+ pr_debug("%s: dcon now %08x\n", __func__, dcon);
chan->dcon = dcon;
chan->xfer_unit = xferunit;
if (chan == NULL)
return -EINVAL;
- pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
+ pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags);
chan->flags = flags;
if (chan == NULL)
return -EINVAL;
- pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
+ pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
chan->op_fn = rtn;
if (chan == NULL)
return -EINVAL;
- pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
+ pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
chan->callback_fn = rtn;
return -EINVAL;
pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
- __FUNCTION__, (int)source, hwcfg, devaddr);
+ __func__, (int)source, hwcfg, devaddr);
chan->source = source;
chan->dev_addr = devaddr;
case S3C2410_DMASRC_HW:
/* source is hardware */
pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
- __FUNCTION__, devaddr, hwcfg);
+ __func__, devaddr, hwcfg);
dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
case S3C2410_DMASRC_MEM:
/* source is memory */
- pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n",
- __FUNCTION__, devaddr, hwcfg);
+ pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
+ __func__, devaddr, hwcfg);
dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);