[PATCH] arm26: fixup asm statement in kernel/fiq.c

Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Acked-by: Ian Molton <spyro@f2s.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

diff --git a/arch/arm26/kernel/fiq.c b/arch/arm26/kernel/fiq.c
index 08a97c9498ff30c93310d934b424ea07e8125e4e..a24272b61f302c5aefc96b7c868b0ae297d9cb4f 100644 (file)
--- a/arch/arm26/kernel/fiq.c
+++ b/arch/arm26/kernel/fiq.c
@@ -104,14 +104,14 @@ void set_fiq_regs(struct pt_regs *regs)
 {
        register unsigned long tmp, tmp2;
        __asm__ volatile (
-       "mov    %0, pc
-       bic     %1, %0, #0x3
-       orr     %1, %1, %3
-       teqp    %1, #0          @ select FIQ mode
-       mov     r0, r0
-       ldmia   %2, {r8 - r14}
-       teqp    %0, #0          @ return to SVC mode
-       mov     r0, r0"
+       "mov    %0, pc                                  \n"
+       "bic    %1, %0, #0x3                            \n"
+       "orr    %1, %1, %3                              \n"
+       "teqp   %1, #0          @ select FIQ mode       \n"
+       "mov    r0, r0                                  \n"
+       "ldmia  %2, {r8 - r14}                          \n"
+       "teqp   %0, #0          @ return to SVC mode    \n"
+       "mov    r0, r0                                  "
        : "=&r" (tmp), "=&r" (tmp2)
        : "r" (&regs->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26)
        /* These registers aren't modified by the above code in a way
@@ -125,14 +125,14 @@ void get_fiq_regs(struct pt_regs *regs)
 {
        register unsigned long tmp, tmp2;
        __asm__ volatile (
-       "mov    %0, pc
-       bic     %1, %0, #0x3
-       orr     %1, %1, %3
-       teqp    %1, #0          @ select FIQ mode
-       mov     r0, r0
-       stmia   %2, {r8 - r14}
-       teqp    %0, #0          @ return to SVC mode
-       mov     r0, r0"
+       "mov    %0, pc                                  \n"
+       "bic    %1, %0, #0x3                            \n"
+       "orr    %1, %1, %3                              \n"
+       "teqp   %1, #0          @ select FIQ mode       \n"
+       "mov    r0, r0                                  \n"
+       "stmia  %2, {r8 - r14}                          \n"
+       "teqp   %0, #0          @ return to SVC mode    \n"
+       "mov    r0, r0                                  "
        : "=&r" (tmp), "=&r" (tmp2)
        : "r" (&regs->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26)
        /* These registers aren't modified by the above code in a way