}
/*
- * Setup windows for PCI+PCIE IO+MAM space
+ * Setup windows for PCI+PCIe IO+MEM space.
*/
- orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE,
- ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP);
- orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE,
- ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP);
- orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE,
+ orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
+ ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
+ orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
+ ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
+ orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
ORION_PCIE_MEM_SIZE, -1);
- orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE,
+ orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
ORION_PCI_MEM_SIZE, -1);
}
****************************************************************************/
static struct map_desc orion_io_desc[] __initdata = {
{
- .virtual = ORION_REGS_BASE,
- .pfn = __phys_to_pfn(ORION_REGS_BASE),
+ .virtual = ORION_REGS_VIRT_BASE,
+ .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE),
.length = ORION_REGS_SIZE,
.type = MT_DEVICE
},
{
- .virtual = ORION_PCIE_IO_BASE,
- .pfn = __phys_to_pfn(ORION_PCIE_IO_BASE),
+ .virtual = ORION_PCIE_IO_VIRT_BASE,
+ .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE),
.length = ORION_PCIE_IO_SIZE,
.type = MT_DEVICE
},
{
- .virtual = ORION_PCI_IO_BASE,
- .pfn = __phys_to_pfn(ORION_PCI_IO_BASE),
+ .virtual = ORION_PCI_IO_VIRT_BASE,
+ .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE),
.length = ORION_PCI_IO_SIZE,
.type = MT_DEVICE
},
{
- .virtual = ORION_PCIE_WA_BASE,
- .pfn = __phys_to_pfn(ORION_PCIE_WA_BASE),
+ .virtual = ORION_PCIE_WA_VIRT_BASE,
+ .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE),
.length = ORION_PCIE_WA_SIZE,
.type = MT_DEVICE
},
static struct resource orion_uart_resources[] = {
{
- .start = UART0_BASE,
- .end = UART0_BASE + 0xff,
+ .start = UART0_PHYS_BASE,
+ .end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
.flags = IORESOURCE_IRQ,
},
{
- .start = UART1_BASE,
- .end = UART1_BASE + 0xff,
+ .start = UART1_PHYS_BASE,
+ .end = UART1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
static struct plat_serial8250_port orion_uart_data[] = {
{
- .mapbase = UART0_BASE,
- .membase = (char *)UART0_BASE,
+ .mapbase = UART0_PHYS_BASE,
+ .membase = (char *)UART0_VIRT_BASE,
.irq = IRQ_ORION_UART0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.uartclk = ORION_TCLK,
},
{
- .mapbase = UART1_BASE,
- .membase = (char *)UART1_BASE,
+ .mapbase = UART1_PHYS_BASE,
+ .membase = (char *)UART1_VIRT_BASE,
.irq = IRQ_ORION_UART1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
static struct resource orion_ehci0_resources[] = {
{
- .start = ORION_USB0_REG_BASE,
- .end = ORION_USB0_REG_BASE + SZ_4K,
+ .start = ORION_USB0_PHYS_BASE,
+ .end = ORION_USB0_PHYS_BASE + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
static struct resource orion_ehci1_resources[] = {
{
- .start = ORION_USB1_REG_BASE,
- .end = ORION_USB1_REG_BASE + SZ_4K,
+ .start = ORION_USB1_PHYS_BASE,
+ .end = ORION_USB1_PHYS_BASE + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
static struct resource orion_eth_shared_resources[] = {
{
- .start = ORION_ETH_REG_BASE,
- .end = ORION_ETH_REG_BASE + 0xffff,
+ .start = ORION_ETH_PHYS_BASE,
+ .end = ORION_ETH_PHYS_BASE + 0xffff,
.flags = IORESOURCE_MEM,
},
};
static struct resource orion_i2c_resources[] = {
{
.name = "i2c base",
- .start = I2C_BASE,
- .end = I2C_BASE + 0x20 -1,
+ .start = I2C_PHYS_BASE,
+ .end = I2C_PHYS_BASE + 0x20 -1,
.flags = IORESOURCE_MEM,
},
{
static struct resource orion_sata_resources[] = {
{
.name = "sata base",
- .start = ORION_SATA_REG_BASE,
- .end = ORION_SATA_REG_BASE + 0x5000 - 1,
+ .start = ORION_SATA_PHYS_BASE,
+ .end = ORION_SATA_PHYS_BASE + 0x5000 - 1,
.flags = IORESOURCE_MEM,
},
{
MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
/* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
- .phys_io = ORION_REGS_BASE,
- .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc,
+ .phys_io = ORION_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.init_machine = db88f5281_init,
.map_io = orion_map_io,
*
* Open a special address decode windows for the PCIE WA.
*/
- orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
- orion_write(ORION_REGS_BASE | 0x20070,
+ orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
+ orion_write(ORION_REGS_VIRT_BASE | 0x20070,
(0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
MACHINE_START(DNS323, "D-Link DNS-323")
/* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
- .phys_io = ORION_REGS_BASE,
- .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
+ .phys_io = ORION_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = dns323_init,
.map_io = orion_map_io,
/*
* Open a special address decode windows for the PCIE WA.
*/
- orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
- orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
+ orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
+ orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/*
MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
- .phys_io = ORION_REGS_BASE,
- .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
+ .phys_io = ORION_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = kurobox_pro_init,
.map_io = orion_map_io,
orion_pcie_id(&dev, &rev);
if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
/* extended register space */
- pcie_addr = ORION_PCIE_WA_BASE;
+ pcie_addr = ORION_PCIE_WA_VIRT_BASE;
pcie_addr |= PCIE_CONF_BUS(bus->number) |
PCIE_CONF_DEV(PCI_SLOT(devfn)) |
PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
*/
res[0].name = "PCI-EX I/O Space";
res[0].flags = IORESOURCE_IO;
- res[0].start = ORION_PCIE_IO_REMAP;
+ res[0].start = ORION_PCIE_IO_BUS_BASE;
res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCIE IO resource failed\n");
*/
res[1].name = "PCI-EX Memory Space";
res[1].flags = IORESOURCE_MEM;
- res[1].start = ORION_PCIE_MEM_BASE;
+ res[1].start = ORION_PCIE_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1]))
panic("Request PCIE Memory resource failed\n");
*/
res[0].name = "PCI I/O Space";
res[0].flags = IORESOURCE_IO;
- res[0].start = ORION_PCI_IO_REMAP;
+ res[0].start = ORION_PCI_IO_BUS_BASE;
res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCI IO resource failed\n");
*/
res[1].name = "PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
- res[1].start = ORION_PCI_MEM_BASE;
+ res[1].start = ORION_PCI_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1]))
panic("Request PCI Memory resource failed\n");
/*
* Open a special address decode windows for the PCIE WA.
*/
- orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
- orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
+ orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
+ orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/*
MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
- .phys_io = ORION_REGS_BASE,
- .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
+ .phys_io = ORION_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = rd88f5182_init,
.map_io = orion_map_io,
* QNAP TS-[12]09 specific power off method via UART1-attached PIC
*/
-#define UART1_REG(x) (UART1_BASE + ((UART_##x) << 2))
+#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
static void qnap_ts209_power_off(void)
{
/*
* Open a special address decode windows for the PCIE WA.
*/
- orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
- orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
+ orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
+ orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/*
MACHINE_START(TS209, "QNAP TS-109/TS-209")
/* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
- .phys_io = ORION_REGS_BASE,
- .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
+ .phys_io = ORION_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = qnap_ts209_init,
.map_io = orion_map_io,
* published by the Free Software Foundation.
*/
+#include <asm/arch/orion.h>
+
.macro addruart,rx
- mov \rx, #0xf1000000
- orr \rx, \rx, #0x00012000
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1 @ MMU enabled?
+ ldreq \rx, =ORION_REGS_PHYS_BASE
+ ldrne \rx, =ORION_REGS_VIRT_BASE
+ orr \rx, \rx, #0x00012000
.endm
#define UART_SHIFT 2
*
* Low-level IRQ helper macros for Orion platforms
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
- *
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#include "orion.h"
-#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE
-#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
+#define pcibios_assign_all_busses() 1
-#define pcibios_assign_all_busses() 1
+#define PCIBIOS_MIN_IO 0x00001000
+#define PCIBIOS_MIN_MEM 0x01000000
+#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE
-#define PCIBIOS_MIN_IO 0x1000
-#define PCIBIOS_MIN_MEM 0x01000000
-#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
-#endif /* _ASM_ARCH_HARDWARE_H */
+#endif
#ifndef __ASM_ARCH_ORION_H__
#define __ASM_ARCH_ORION_H__
-/*******************************************************************************
+/*****************************************************************************
* Orion Address Map
- * Use the same mapping (1:1 virtual:physical) of internal registers and
- * PCI system (PCI+PCIE) for all machines.
- * Each machine defines the rest of its mapping (e.g. device bus flashes)
- ******************************************************************************/
-#define ORION_REGS_BASE 0xf1000000
+ *
+ * virt phys size
+ * f0000000 f0000000 16M PCIe WA space (Orion-NAS only)
+ * f1000000 f1000000 1M on-chip peripheral registers
+ * f2000000 f2000000 1M PCIe I/O space
+ * f2100000 f2100000 1M PCI I/O space
+ ****************************************************************************/
+#define ORION_REGS_PHYS_BASE 0xf1000000
+#define ORION_REGS_VIRT_BASE 0xf1000000
#define ORION_REGS_SIZE SZ_1M
-#define ORION_PCI_SYS_MEM_BASE 0xe0000000
-#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE
-#define ORION_PCIE_MEM_SIZE SZ_128M
-#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
-#define ORION_PCI_MEM_SIZE SZ_128M
-
-#define ORION_PCI_SYS_IO_BASE 0xf2000000
-#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
+#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
+#define ORION_PCIE_IO_VIRT_BASE 0xf2000000
+#define ORION_PCIE_IO_BUS_BASE 0x00000000
#define ORION_PCIE_IO_SIZE SZ_1M
-#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
-#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
+
+#define ORION_PCI_IO_PHYS_BASE 0xf2100000
+#define ORION_PCI_IO_VIRT_BASE 0xf2100000
+#define ORION_PCI_IO_BUS_BASE 0x00100000
#define ORION_PCI_IO_SIZE SZ_1M
-#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
+
/* Relevant only for Orion-NAS */
-#define ORION_PCIE_WA_BASE 0xf0000000
+#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
+#define ORION_PCIE_WA_VIRT_BASE 0xf0000000
#define ORION_PCIE_WA_SIZE SZ_16M
+#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000
+#define ORION_PCIE_MEM_SIZE SZ_128M
+
+#define ORION_PCI_MEM_PHYS_BASE 0xe8000000
+#define ORION_PCI_MEM_SIZE SZ_128M
+
/*******************************************************************************
* Supported Devices & Revisions
******************************************************************************/
/*******************************************************************************
* Orion Registers Map
******************************************************************************/
-#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000)
-#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000)
-#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000)
-#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000)
-#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000)
-#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000)
-#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000)
-#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000)
-#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000)
-
-#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x))
-#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x))
-#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x))
-#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x))
-#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x))
-#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x))
-#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x))
-#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x))
-#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x))
+#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000)
+#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x))
+
+#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000)
+#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000)
+#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x))
+#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000)
+#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000)
+#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000)
+#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100)
+#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100)
+
+#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000)
+#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x))
+
+#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000)
+#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x))
+
+#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000)
+#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x))
+
+#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000)
+#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000)
+#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x))
+
+#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000)
+#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000)
+#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x))
+
+#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000)
+#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000)
+#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x))
+
+#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000)
+#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000)
+#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x))
/*******************************************************************************
* Device Bus Registers
#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
-#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
-#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
-#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
#define GPIO_MAX 32
/***************************************************************************
#include <asm/arch/orion.h>
-#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14))
-#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0))
+#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
+#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
#define LSR_THRE 0x20
projects / linux-2.6 / commitdiff