{
register_intc_controller(&intc_desc);
}
+
+void __init plat_mem_setup(void)
+{
+ /* Register CPU#0 URAM space as Node 1 */
+ setup_bootmem_node(1, 0x145f0000, 0x14610000); /* CPU0 */
+
+#if 0
+ /* XXX: Not yet.. */
+ setup_bootmem_node(2, 0x14df0000, 0x14e10000); /* CPU1 */
+ setup_bootmem_node(3, 0x155f0000, 0x15610000); /* CPU2 */
+ setup_bootmem_node(4, 0x15df0000, 0x15e10000); /* CPU3 */
+ setup_bootmem_node(5, 0x16000000, 0x16020000); /* CSM */
+#endif
+}
select CPU_SH4A
select CPU_SHX3
select CPU_HAS_INTC_IRQ
+ select ARCH_SPARSEMEM_ENABLE
+ select SYS_SUPPORTS_NUMA
# SH4AL-DSP Processor Support
config MAX_ACTIVE_REGIONS
int
+ default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM)
default "1"