Add support for Seeq 8003 on Challenge S Mezz board.

Thanks to Jö Fahlke for donating hardware.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Forward porting of Ladis' 2.4 patch.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

diff --git a/drivers/net/sgiseeq.c b/drivers/net/sgiseeq.c
index d8c9c5d66d4fb7a94ddab84444e521cd3221e76c..1fc77300b0552d688d14148ba4def8d82148e0ca 100644 (file)
--- a/drivers/net/sgiseeq.c
+++ b/drivers/net/sgiseeq.c
@@ -624,7 +624,7 @@ static inline void setup_rx_ring(struct sgiseeq_rx_desc *buf, int nbufs)
 
 #define ALIGNED(x)  ((((unsigned long)(x)) + 0xf) & ~(0xf))
 
-static int sgiseeq_init(struct hpc3_regs* hpcregs, int irq)
+static int sgiseeq_init(struct hpc3_regs* hpcregs, int irq, int has_eeprom)
 {
        struct sgiseeq_init_block *sr;
        struct sgiseeq_private *sp;
@@ -650,7 +650,9 @@ static int sgiseeq_init(struct hpc3_regs* hpcregs, int irq)
 
 #define EADDR_NVOFS     250
        for (i = 0; i < 3; i++) {
-               unsigned short tmp = ip22_nvram_read(EADDR_NVOFS / 2 + i);
+               unsigned short tmp = has_eeprom ?
+                       ip22_eeprom_read(&hpcregs->eeprom, EADDR_NVOFS / 2+i) :
+                       ip22_nvram_read(EADDR_NVOFS / 2+i);
 
                dev->dev_addr[2 * i]     = tmp >> 8;
                dev->dev_addr[2 * i + 1] = tmp & 0xff;
@@ -678,6 +680,11 @@ static int sgiseeq_init(struct hpc3_regs* hpcregs, int irq)
        setup_rx_ring(sp->rx_desc, SEEQ_RX_BUFFERS);
        setup_tx_ring(sp->tx_desc, SEEQ_TX_BUFFERS);
 
+       /* Setup PIO and DMA transfer timing */
+       sp->hregs->pconfig = 0x161;
+       sp->hregs->dconfig = HPC3_EDCFG_FIRQ | HPC3_EDCFG_FEOP |
+                            HPC3_EDCFG_FRXDC | HPC3_EDCFG_PTO | 0x026;
+
        /* Setup PIO and DMA transfer timing */
        sp->hregs->pconfig = 0x161;
        sp->hregs->dconfig = HPC3_EDCFG_FIRQ | HPC3_EDCFG_FEOP |
@@ -729,8 +736,23 @@ err_out:
 
 static int __init sgiseeq_probe(void)
 {
+       unsigned int tmp, ret1, ret2 = 0;
+
        /* On board adapter on 1st HPC is always present */
-       return sgiseeq_init(hpc3c0, SGI_ENET_IRQ);
+       ret1 = sgiseeq_init(hpc3c0, SGI_ENET_IRQ, 0);
+       /* Let's see if second HPC is there */
+       if (!(ip22_is_fullhouse()) &&
+           get_dbe(tmp, (unsigned int *)&hpc3c1->pbdma[1]) == 0) {
+               sgimc->giopar |= SGIMC_GIOPAR_MASTEREXP1 |
+                                SGIMC_GIOPAR_EXP164 |
+                                SGIMC_GIOPAR_HPC264;
+               hpc3c1->pbus_piocfg[0][0] = 0x3ffff;
+               /* interrupt/config register on Challenge S Mezz board */
+               hpc3c1->pbus_extregs[0][0] = 0x30;
+               ret2 = sgiseeq_init(hpc3c1, SGI_GIO_0_IRQ, 1);
+       }
+
+       return (ret1 & ret2) ? ret1 : 0;
 }
 
 static void __exit sgiseeq_exit(void)