offset += dev_size;
}
mtd->type = MTD_NORFLASH;
+ mtd->writesize = 1;
mtd->flags = MTD_CAP_NORFLASH;
mtd->name = map->name;
mtd->erase = amd_flash_erase;
mtd->resume = cfi_amdstd_resume;
mtd->flags = MTD_CAP_NORFLASH;
mtd->name = map->name;
+ mtd->writesize = 1;
if (cfi->cfi_mode==CFI_MODE_CFI){
unsigned char bootloc;
mtd->suspend = sharp_suspend;
mtd->resume = sharp_resume;
mtd->flags = MTD_CAP_NORFLASH;
+ mtd->writesize = 1;
mtd->name = map->name;
memset(sharp, 0, sizeof(*sharp));
printk ("%s: This looks like a LART board to me.\n",module_name);
mtd.name = module_name;
mtd.type = MTD_NORFLASH;
+ mtd.writesize = 1;
mtd.flags = MTD_CAP_NORFLASH;
mtd.size = FLASH_BLOCKSIZE_PARAM * FLASH_NUMBLOCKS_16m_PARAM + FLASH_BLOCKSIZE_MAIN * FLASH_NUMBLOCKS_16m_MAIN;
mtd.erasesize = FLASH_BLOCKSIZE_MAIN;
flash->mtd.name = spi->dev.bus_id;
flash->mtd.type = MTD_NORFLASH;
+ flash->mtd.writesize = 1;
flash->mtd.flags = MTD_CAP_NORFLASH;
flash->mtd.size = info->sector_size * info->n_sectors;
flash->mtd.erasesize = info->sector_size;
mtd->type = MTD_GENERIC_TYPE;
mtd->flags = MTD_CAP_RAM;
mtd->size = size;
+ mtd->writesize = 1;
mtd->erasesize = MTDRAM_ERASE_SIZE;
mtd->priv = mapped_address;
{
int i;
+ BUG_ON(mtd->writesize == 0);
mutex_lock(&mtd_table_mutex);
for (i=0; i < MAX_MTD_DEVICES; i++)
* information below if they desire
*/
u_int32_t erasesize;
- /* Smallest availlable size for writing to the device. For NAND,
- * this is the page size, for some NOR chips, the size of ECC
- * covered blocks.
+ /* Minimal writable flash unit size. In case of NOR flash it is 1 (even
+ * though individual bits can be cleared), in case of NAND flash it is
+ * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR
+ * it is of ECC block size, etc. It is illegal to have writesize = 0.
+ * Any driver registering a struct mtd_info must ensure a writesize of
+ * 1 or larger.
*/
u_int32_t writesize;