]> err.no Git - linux-2.6/commitdiff
[ARM] 4832/2: Support AC97CLK on PXA3xx via the clock API
authorMark Brown <broonie@sirena.org.uk>
Tue, 4 Mar 2008 10:14:23 +0000 (11:14 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Sat, 19 Apr 2008 10:29:03 +0000 (11:29 +0100)
The AC97 clock rate on PXA3xx is generated with a configurable divider
from sys_pll.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mach-pxa/pxa3xx.c

index 54c9e8371a219d870659988d161d05cf57c4f634..93f3236b410041c3a6cdccbfcb92801afb4afb8b 100644 (file)
@@ -109,6 +109,25 @@ unsigned int pxa3xx_get_memclk_frequency_10khz(void)
        return (clk / 10000);
 }
 
+/*
+ * Return the current AC97 clock frequency.
+ */
+static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
+{
+       unsigned long rate = 312000000;
+       unsigned long ac97_div;
+
+       ac97_div = AC97_DIV;
+
+       /* This may loose precision for some rates but won't for the
+        * standard 24.576MHz.
+        */
+       rate /= (ac97_div >> 12) & 0x7fff;
+       rate *= (ac97_div & 0xfff);
+
+       return rate;
+}
+
 /*
  * Return the current HSIO bus clock frequency
  */
@@ -156,6 +175,12 @@ static const struct clkops clk_pxa3xx_hsio_ops = {
        .getrate        = clk_pxa3xx_hsio_getrate,
 };
 
+static const struct clkops clk_pxa3xx_ac97_ops = {
+       .enable         = clk_pxa3xx_cken_enable,
+       .disable        = clk_pxa3xx_cken_disable,
+       .getrate        = clk_pxa3xx_ac97_getrate,
+};
+
 static void clk_pout_enable(struct clk *clk)
 {
        OSCC |= OSCC_PEN;
@@ -197,8 +222,9 @@ static struct clk pxa3xx_clks[] = {
                .delay          = 70,
        },
 
-       PXA3xx_CK("LCDCLK", LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
-       PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
+       PXA3xx_CK("LCDCLK",  LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
+       PXA3xx_CK("CAMCLK",  CAMERA, &clk_pxa3xx_hsio_ops, NULL),
+       PXA3xx_CK("AC97CLK", AC97,   &clk_pxa3xx_ac97_ops, NULL),
 
        PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
        PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),